IEEE Computer Society

Sunday, June 20, 2004
Held in conjunction with ISCA-31, Munich Germany, June 19-23, 2004


Workshop Program

Call for Papers

Program Committee

Important Dates

Paper Submission


If you are looking for the home page of TACS-2 for 2005, please click here

Many analysts suggest that increasing power density and resulting difficulties in managing on-chip temperatures are some of the most urgent obstacles to continued scaling of VLSI systems within the next five to ten years. Just as has been done before for power-aware computing, "temperature-aware" computing must be approached not just from the packaging and circuit-design communities, but also from the processor- and systems- architecture communities. Many techniques for managing operating temperature will use power-management techniques, but possibly in different ways than for energy efficiency. There is growing interest in cooling solutions from the processor- and systems-architecture domains, as evidenced by recent work on fetch throttling, dynamic voltage scaling, and process scheduling in response to thermal stress; and some progress has been made on modeling infrastructure for this kind of research. But research so far has only scratched the surface of what is possible.

This workshop will serve as a forum to explore a broad spectrum of topics pertaining to temperature-aware computer architecture, for researchers to exchange ideas and initiate collaborations, and will help to establish temperature-aware computing as an important research topic in its own right.

Site Updated: 1 July 2004