IEEE Computer Society

Sunday, June 5, 2005
Held in conjunction with ISCA-32, Madison, WI, USA, June 4-8, 2005


Workshop Program

Call for Papers

Program Committee

Important Dates

Paper Submission

Many analysts suggest that increasing power density and resulting difficulties in managing on-chip temperatures are some of the most urgent obstacles to continued scaling of VLSI systems within the next five to ten years. Just as has been done before for power-aware computing, "temperature-aware" computing must be approached not just from the packaging and circuit-design communities, but also from the processor- and systems- architecture communities. Many techniques for managing operating temperature will use power-management techniques, but possibly in different ways than for energy efficiency. There is growing interest in cooling solutions from the processor- and systems-architecture domains, as evidenced by recent work on fetch throttling, dynamic voltage scaling, and process scheduling in response to thermal stress; and some progress has been made on modeling infrastructure for this kind of research. But research so far has only scratched the surface of what is possible. This topic area presents a wide-open field for new research, with lots of "low-hanging fruit", and interesting opportunities for wide-ranging inter-disciplinary work.

This workshop will serve as a forum to explore a broad spectrum of topics pertaining to temperature-aware computer systems, for researchers from multiple fields to exchange ideas and initiate collaborations, and to continue establishing temperature-aware computing as an important research topic in its own right. Contributions from all aspects of temperature-aware design are encouraged, related topics like reliability, leakage, thermal sensors, etc.  We especially seek to stimulate collaboration between architects and thermal engineers! In fact, the goal of this workshop is to stimulate the widest possible collaboration among architects and other engineers on topics related to temperature-aware design.

For this year's program, we are pleased to present five papers spanning a range of topics in temperature-aware architecture.  We will also have a panel discussion to explore important research topics, and a keynote by Chandrakant D. Patel, Distinguished Technologist at HP Labs, on the topic of "Smart Chip, System and Data Center: Dynamic Provisioning of Power and Cooling from Chip Core to the Cooling Tower."

This is the second year of the TACS workshop.