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2004 Papers:
  • D. Citron. "Exploiting Low Entropy to Reduce Wire Delay." Volume 3, Jan. 2004. [Go to IEEE Xplore]
  • A. Singh, W. J. Dally, B. Towles, A. K. Gupta. "Globally Adaptive Load-Balanced Routing on Tori." Volume 3, Mar. 2004. [Go to IEEE Xplore]
  • M. E. Gomez, J. Duato, J. Flich, P. Lopez, A. Robles, N. A. Nordbotten, O. Lysne, T. Skeie. "An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori." Volume 3, May. 2004. [Go to IEEE Xplore]
  • J. M. Stine, N. P. Carter. "Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction." Volume 3, Jun. 2004. [Go to IEEE Xplore]
  • B. Robatmili, N. Yazdani, S. Sardashti, M. Nourani. "Thread-Sensitive Instruction Issue for SMT Processors." Volume 3, Aug. 2004. [Go to IEEE Xplore]
  • Y. Luo, L. K. John. "Efficiently Evaluating Speedup Using Sampled Processor Simulation." Volume 3, Sep. 2004. [Go to IEEE Xplore]
  • L. Ceze, K. Strauss, J. Tuck, J. Renau, J. Torrellas. "CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction." Volume 3, Dec. 2004. [Go to IEEE Xplore]
  • A. Singh, W. J. Dally. "Buffer and Delay Bounds in High Radix Interconnection Networks." Volume 3, Dec. 2004. [Go to IEEE Xplore]
  • A. L. Holloway, G. S. Sohi. "Characterization of Problem Stores." Volume 3, Dec. 2004. [Go to IEEE Xplore]

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