Computer Architecture Letters

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2008 Papers

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2007 Papers:

A. Biswas, P. Racunas, J. Emer, and S. Mukherjee. "Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal." Computer Architecture Letters, vol. 6, Dec. 2007. [Go to IEEE Xplore]
S. Cho and R. Melhem. "Corollaries to Amdahl's Law for Energy." Computer Architecture Letters, vol. 6, Dec. 2007. [Go to IEEE Xplore]
S. L. Min, J. H. Yoon, E. H. Nam, Y. J. Seong, H. Kim, B. Kim, and Y. Cho. "Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture." Computer Architecture Letters, vol. 6, Dec. 2007. [Go to IEEE Xplore]
J. Flich and J. Duato. "Logic-Based Distributed Routing for NoCs." Computer Architecture Letters, vol. 6, Nov. 2007. [Go to IEEE Xplore]
A. Roth. "Physical Register Reference Counting." Computer Architecture Letters, vol. 6, Oct. 2007. [Go to IEEE Xplore]
G. Yalcun and O. Ergin. "Using Tag-Match Comparators for Detecting Soft Errors. Computer Architecture Letters, vol. 6, Oct. 2007. [Go to IEEE Xplore]
R. Sendag, J. Yi, and P.-f. Chuang. "Branch Misprediction Prediction: Complementary Branch Predictors." Computer Architecture Letters, vol. 6, Sep. 2007. [Go to IEEE Xplore]
D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. Penry, O. Temam, and N. Vachharajani. "UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development." Computer Architecture Letters, vol. 6, Aug. 2007. [Go to IEEE Xplore]
X. Xiao and J. Lee. "A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip." Computer Architecture Letters, vol. 6, Aug. 2007. [Go to IEEE Xplore]
J. Kim, J. Balfour, and W. Dally. "Flattened Butterfly Topology for On-Chip Networks." Computer Architecture Letters, vol. 6, July 2007. [Go to IEEE Xplore]
A. Das, S. Ozdemir, G. Memik, J. Zambreno, and A. Choudhary. "Microarchitectures for Managing Chip Revenues under Process Variations." Computer Architecture Letters, vol. 6, June 2007. [Go to IEEE Xplore]
J. Zebchuk and A. Moshovos. "A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy." Computer Architecture Letters, vol. 6, June 2007. [Go to IEEE Xplore]
J. Joao, O. Mutlu, H. Kim, and Y. Patt. "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters, vol. 6, May 2007. [Go to IEEE Xplore]
Z. Guz, I. Keidar, A. Kolodny, and U. Weiser. "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007. [Go to IEEE Xplore]
Y. Etsion and D. G. Feitelson, "Probabilistic Prediction of Temporal Locality," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007. [Go to IEEE Xplore]
S. Kodakara, J. Kim, D. Lilja, D. Hawkins, W.-C. Hsu, P.-C. Yew, "CIM: A Reliable Metric for Evaluating Program Phase Classifications," IEEE Computer Architecture Letters, vol. 6, no. 1, Apr. 2007. [Go to IEEE Xplore]
M. Moreto Planas, F. Cazorla, A. Ramirez, M. Valero, "Explaining Dynamic Cache Partitioning Speed Ups," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007. [Go to IEEE Xplore]
N. Enright Jerger, M. Lipasti, L.-S. Peh, "Circuit-Switched Coherence," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007. [Go to IEEE Xplore]
W. R. Dieter, A. Kaveti, H. G. Dietz, "Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007. [Go to IEEE Xplore]

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