Thursday, April 30, 2009
Jason Mars
Advisor: Mary Lou Soffa
Attending Faculty: Kim Hazelwood
OLSSON 236D, 14:00:00
A Master's Project Presentation
A General Pattern Based Seculation Framework To Enable Satellite Optimization
ABSTRACT
With the proliferation of multicore architectures new opportunities exists for compilation techniques both static and dynamic. Taking advantage of these opportunities with binary-level dynamic optimizers has proven to be quite challenging and such techniques are few. In this paper, we present a general pattern based speculation framework that can be used in emph{Satellite Optimizers}. These optimizers takes advantage of the available parallelism on multicore architecture to offload the necessary monitoring and analysis, and unobtrusively implement dynamic optimization techniques. In this work we present a novel approach to better use the extra processing availible and hardware features for the speculative prediciton tasks required for satellite optimizations. This general framework we call emph{Satellite Speculation}, uses pattern recognition dynamically to perform phase detection and steer speculative decisions, while self tuning to automatically fit the granulairty of monitored behavior pattern. This paper describes our speculative prediction framework for satellite optimizers and shows the key factors invovled in adapting and customizing this general approach to apply different dynamic optimizations. To evaluate our approach we adapt our Satellite Speculation engine to two separate common online optimization goals: emph{Trace Selection} and emph{Dynamic Software Cache Prefetching}. Using the SPEC2006 benchmark suite we compared the common trace selection approach, Next Executing Tail (NET), to our Satellite Speculation. Using our approach we are able to select traces that cover 33% more dynamic instructions, and executes 55% less compensation code. Using the same general speculation framework for software cache prefetcing, we reduce the number of cache misses in our simulator by an average of 26% and in our best case our technique reduces the miss rate by 84%, while using an aggressive hardware stride prefetcher baseline.