Wednesday, October 21, 2009
Clinton Smullen IV
Chair: Kevin Skadron; Mircea Stan, Bill Wulf and Moin Qureshi
Advisor: Sudhanva Gurumurthi
Olsson Hall, Conference Room 228E, 09:00:00
A Ph.D. Proposal
Designing Giga-scale On-chip Memory Systems
ABSTRACT
The multi-core era heralds the integration of increasing numbers of cores on-chip. However, few real-world programs are entirely compute bound, limited by either the effective memory latency or bandwidth. Ultimately, the speedup that may be obtained by the addition of more cores is limited, regardless of how parallel the software may be, as off-chip communication is unavoidable for real-world workloads.
Adding additional on-die cache is expensive, both in terms of area and manufacturing cost. To alleviate this problem, proposals have been made to reintroduce caches placed on separate dies, oftentimes using new 3D die stacking technology, rather than traditional multi-chip modules. As the separate dies are not constrained by manufacturing requirements for the core die, it is feasible to use a wider range of technologies to design these caches, including commodity DRAM and non-volatile memory. Commodity DRAM can provide a 16x increase in density over SRAM while significantly lowering total power consumption, making it possible to integrate 256 MB or more memory on-chip. However, traditional cache designs do not scale to such large sizes, and it is not possible to fit all of main memory on-chip.
My proposal is to look at the design of on-chip architectures for taking advantage of these large on-chip memories, focusing in particular on the use of commodity DRAM. These designs include using the on-chip memory as either a software- or hardware-managed extension to main memory, as well as new approaches for designing very large caches.