From bogus@does.not.exist.com Wed Mar 22 16:03:59 2006 From: bogus@does.not.exist.com () Date: Wed Mar 22 16:04:09 2006 Subject: No subject Message-ID: power.icache_power -> Icache power.dcache_power -> Dcache power.bpred_power -> Bpred etc... But plenty of them aren't so simple matchings. My first question is, how is the L2 cache divided into three functional units? What functions are performed by "left", "right", and "bottom"? Sim-Wattch's default configuration has only power.dcache2_power. Second, because the simulator used in the paper has augmented the centralized RUU into real issue queues, I have a difficult time getting numbers for IntQ and FPQ. In addition, the Wattch power numbers don't seem to separate integer and floating point registers, nor do they distinguish between floating-point addition and floating-point multiplication. To get started here and make sure I can get some realistic results with HotSpot, I'm inclined to edit the floorplan and combine pieces such as IntReg+FPReg or FPAdd+FPMul back into monolithic units. Certainly, to accurately model modern processors, later on I should make sure to later on simulate real issues queues and more separated structures. But just to get started for this week, would it make sense to hack things together (no real issues queues, and some separate structures made monolithic) and still hope to get some reasonable sanity check numbers out? Lastly, how should I get power numbers for ITB and DTB, which I assume are the Integer TLB and Data TLB? And what are "IntMap" and "FPMap"? -James