From fargh232 at student.liu.se  Wed Jul 15 06:48:13 2009
From: fargh232 at student.liu.se (Farrokh Ghani Zadegan)
Date: Wed, 15 Jul 2009 15:48:13 +0200
Subject: [Hotspot] 3D Chip Simulation
Message-ID: <004201ca0552$e6df9530$b49ebf90$@liu.se>

Hi!

 

As my first experiment, I'm trying to use HotSpot to get the thermal profile
of a simple 3D chip which has three layers: two layers of cache and one
layer containing five functional units. In the HOWTO file (above the section
"The grid model - 3-D stacking capability") it is stated that in order to
keep the cells cubic, the number of Z-layers should also be increased when
we use a fine mesh. Now using a 64x64 grid, I'd like to know which is
better: Still mentioning three layers in the LCF file or breaking them down
into many smaller layers- e.g. 16 identical copies of each layer stacked on
top of each other.

 

Regards,

Farrokh Ghani Zadegan

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From wh6p at cms.mail.virginia.edu  Wed Jul 15 08:08:03 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Wed, 15 Jul 2009 11:08:03 -0400
Subject: [Hotspot] 3D Chip Simulation
In-Reply-To: <004201ca0552$e6df9530$b49ebf90$@liu.se>
References: <004201ca0552$e6df9530$b49ebf90$@liu.se>
Message-ID: <57121873FFB3D24C93D3447F@mstu1>

Hi,

I would suggest first try without more discretization on 
the z direction. As long as your cell side dimensions (x 
and y) are not orders of magnitude larger than the 
thickness, this should be accurate enough.

In general, going up to very fine mesh (e.g. >64x64) 
wouldn't help the actual accuracy of the temperature 
estimation, since your power estimation is a lumped sum and 
is not at the same granularity.

Hope this helps,

-Wei

--On Wednesday, July 15, 2009 3:48 PM +0200 Farrokh Ghani 
Zadegan <fargh232 at student.liu.se> wrote:

>
>
> Hi!
>
>
>
> As my first experiment, I'm trying to use HotSpot to get
> the thermal profile of a simple 3D chip which has three
> layers: two layers of cache and one layer containing five
> functional units. In the HOWTO file (above the section
> "The grid model - 3-D stacking capability") it is stated
> that in order to keep the cells cubic, the number of
> Z-layers should also be increased when we use a fine
> mesh. Now using a 64x64 grid, I'd like to know which is
> better: Still mentioning three layers in the LCF file or
> breaking them down into many smaller layers- e.g. 16
> identical copies of each layer stacked on top of each
> other.
>
>
>
> Regards,
>
> Farrokh Ghani Zadegan





From ofosho at gatech.edu  Thu Jul 16 07:34:02 2009
From: ofosho at gatech.edu (Omar Chanouha)
Date: Thu, 16 Jul 2009 10:34:02 -0400
Subject: [Hotspot] A Few Questions
Message-ID: <130f58620907160734y26c32bbfr1f1688a966e3b5df@mail.gmail.com>

Hey Everyone,

I am a Georgia Tech student trying to use Hotspot to conduct some
research for a special problem. Specifically, I am trying to test the
feasibility of malicious QoS attacks on embedded systems with 2 or
more processors. In order to do this I need to be able to model
multiple processors next to each other.

1) Is there a way to model a floorplan with more than one processor
using hotspot? If not, could someone help me get started changing the
source to be able to do this? I was thinking that I would build upon
existing single processor floorplans by doubling the components and
adding some dead space. Any thoughts on that?

2) How was the power trace file created? I am assuming that it wasn't
done manually?

3) I am assuming that Hotfloorplan is not useful in my scenario
because I want to simulate chips that exist, and hotfloorplan is
intended to optimize new designs. Is that correct?

4) Does anyone have floorplans for pre-existing chips that I could
see? Even if it is old/dated I would still like to see how an actual
chip is modeled as a Hotspot floorplan for reference purposes.

Thanks,

-O

From wh6p at cms.mail.virginia.edu  Thu Jul 16 10:26:39 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Thu, 16 Jul 2009 13:26:39 -0400
Subject: [Hotspot] A Few Questions
In-Reply-To: <130f58620907160734y26c32bbfr1f1688a966e3b5df@mail.gmail.com>
References: <130f58620907160734y26c32bbfr1f1688a966e3b5df@ma
 il.gmail.com>
Message-ID: <52EE0C479AFA745AABC28304@mstu1>

Hi Omar, please see below...
>
> 1) Is there a way to model a floorplan with more than one
> processor using hotspot? If not, could someone help me
> get started changing the source to be able to do this? I
> was thinking that I would build upon existing single
> processor floorplans by doubling the components and
> adding some dead space. Any thoughts on that?

As long as you have a floorplan and a power trace, HotSpot 
should be able to model temperatures for you. No need to 
change the source code, just configure another .flp file 
using the file format provided. How to add more than one 
core into a single silicon is a research question that is 
not directly related to the HotSPot model. What you suggest 
is one possible way to do that, but please keep in mind 
that the max die size is sort of fixed due to the area 
limit of a reticle, so you might want to shrink the size of 
each "core" according to CMOS scaling to fit the limited 
die area.

>
> 2) How was the power trace file created? I am assuming
> that it wasn't done manually?

Inside HotSpot release, there is a file, sim-template.c, 
that shows a template of how to integrated HotSpot with 
other tools such as SimpleScalar and Wattch. You'll have to 
implement the details according to you needs.

>
> 3) I am assuming that Hotfloorplan is not useful in my
> scenario because I want to simulate chips that exist, and
> hotfloorplan is intended to optimize new designs. Is that
> correct?

If you just want to assemble several "cores" into on chip, 
Hotfloorplan might not be useful. However, if you have an 
idea of what units in your microarchtecture (or cores in 
your CMP design) and have a rough area estimation for them 
with some interconnection info among the units, 
Hotfloorplan will help you find a thermally optimal 
floorplan with minimum communication delay.

>
> 4) Does anyone have floorplans for pre-existing chips
> that I could see? Even if it is old/dated I would still
> like to see how an actual chip is modeled as a Hotspot
> floorplan for reference purposes.

There is an example floorplan, ev6.flp, which is extracted 
from Alpha 21364. It should help you to jump start. I am 
sure there are many chip photographs with dimensions on the 
Web as well. In the release, there are also many other 
resources that might be helpful to you, so please be sure 
to read the READMEs and HOWTOs, and play with the sample 
files.

Hope it helps. Have fun with HotSpot :)

-Wei


From ofosho at gatech.edu  Thu Jul 16 12:05:21 2009
From: ofosho at gatech.edu (Omar Chanouha)
Date: Thu, 16 Jul 2009 15:05:21 -0400
Subject: [Hotspot] A Few Questions
In-Reply-To: <52EE0C479AFA745AABC28304@mstu1>
References: <130f58620907160734y26c32bbfr1f1688a966e3b5df@mail.gmail.com>
	<52EE0C479AFA745AABC28304@mstu1>
Message-ID: <130f58620907161205i7e20eed8x67e90b4244b94a02@mail.gmail.com>

Thanks for the quick reply Wei. After writing the initial email I
realized that it was a little confusing. My idea to add space will not
work because as you said it is a way of having multiple cores. I need
to be able to simulate multiple chips. Meaning, 2 dies, 2 heatsinks,
etc. next to each other. Is this possible? The reason for this is that
I would like to see what effect adjacent processors can have on each
other during a thermal attack. If it is not currently possible, where
would I begin to add this functionality?

Thanks,

-O

On Thu, Jul 16, 2009 at 1:26 PM, Wei Huang<wh6p at cms.mail.virginia.edu> wrote:
> Hi Omar, please see below...
>>
>> 1) Is there a way to model a floorplan with more than one
>> processor using hotspot? If not, could someone help me
>> get started changing the source to be able to do this? I
>> was thinking that I would build upon existing single
>> processor floorplans by doubling the components and
>> adding some dead space. Any thoughts on that?
>
> As long as you have a floorplan and a power trace, HotSpot should be able to
> model temperatures for you. No need to change the source code, just
> configure another .flp file using the file format provided. How to add more
> than one core into a single silicon is a research question that is not
> directly related to the HotSPot model. What you suggest is one possible way
> to do that, but please keep in mind that the max die size is sort of fixed
> due to the area limit of a reticle, so you might want to shrink the size of
> each "core" according to CMOS scaling to fit the limited die area.
>
>>
>> 2) How was the power trace file created? I am assuming
>> that it wasn't done manually?
>
> Inside HotSpot release, there is a file, sim-template.c, that shows a
> template of how to integrated HotSpot with other tools such as SimpleScalar
> and Wattch. You'll have to implement the details according to you needs.
>
>>
>> 3) I am assuming that Hotfloorplan is not useful in my
>> scenario because I want to simulate chips that exist, and
>> hotfloorplan is intended to optimize new designs. Is that
>> correct?
>
> If you just want to assemble several "cores" into on chip, Hotfloorplan
> might not be useful. However, if you have an idea of what units in your
> microarchtecture (or cores in your CMP design) and have a rough area
> estimation for them with some interconnection info among the units,
> Hotfloorplan will help you find a thermally optimal floorplan with minimum
> communication delay.
>
>>
>> 4) Does anyone have floorplans for pre-existing chips
>> that I could see? Even if it is old/dated I would still
>> like to see how an actual chip is modeled as a Hotspot
>> floorplan for reference purposes.
>
> There is an example floorplan, ev6.flp, which is extracted from Alpha 21364.
> It should help you to jump start. I am sure there are many chip photographs
> with dimensions on the Web as well. In the release, there are also many
> other resources that might be helpful to you, so please be sure to read the
> READMEs and HOWTOs, and play with the sample files.
>
> Hope it helps. Have fun with HotSpot :)
>
> -Wei
>
>

From wh6p at cms.mail.virginia.edu  Thu Jul 16 12:23:54 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Thu, 16 Jul 2009 15:23:54 -0400
Subject: [Hotspot] A Few Questions
In-Reply-To: <130f58620907161205i7e20eed8x67e90b4244b94a02@mail.gmail.com>
References: <130f58620907160734y26c32bbfr1f1688a966e3b5df@mai
	l.gmail.com>	 <52EE0C479AFA745AABC28304@mstu1>
	<130f58620907161205i7e20eed8x67e90b4244b94a02@mail.gmail.com>
Message-ID: <DE8D0A45E7D5E90B3CAAEBC9@mstu1>

Do you mean something like a MCM (multi-chip module in the 
same package), or multiple chip on a PCB with a box? These 
are currently beyond HotSpot's modeling capability. As far 
as I know, there are no compact models like HotSpot at the 
MCM and box levels. There are commercial tools like 
FloTherm that might be able to model heat transfer and air 
convection inside a computer box using finite element 
methods, but those might be too slow to model chip-level 
thermal details.

Professor Bianchini's group at Rutgers University has a 
model called Mercury that models the heat transfer by 
convection among multiple chips/components inside something 
like a box, but they treat each chip as a single node. 
Maybe combining Mercury and HotSpot is a way to approach 
your needs, but that includes non-trivial amount of work.

There is also some work from Professor Zhao Zhang's group 
at Iowa State on processor's thermal impact on DRAM, if I 
remember correctly. So this might also be interesting to 
you.

-Wei

--On Thursday, July 16, 2009 3:05 PM -0400 Omar Chanouha 
<ofosho at gatech.edu> wrote:

> Thanks for the quick reply Wei. After writing the initial
> email I realized that it was a little confusing. My idea
> to add space will not work because as you said it is a
> way of having multiple cores. I need to be able to
> simulate multiple chips. Meaning, 2 dies, 2 heatsinks,
> etc. next to each other. Is this possible? The reason for
> this is that I would like to see what effect adjacent
> processors can have on each other during a thermal
> attack. If it is not currently possible, where would I
> begin to add this functionality?
>
> Thanks,
>
> -O
>
> On Thu, Jul 16, 2009 at 1:26 PM, Wei
> Huang<wh6p at cms.mail.virginia.edu> wrote:
>> Hi Omar, please see below...
>>>
>>> 1) Is there a way to model a floorplan with more than
>>> one processor using hotspot? If not, could someone help
>>> me get started changing the source to be able to do
>>> this? I was thinking that I would build upon existing
>>> single processor floorplans by doubling the components
>>> and adding some dead space. Any thoughts on that?
>>
>> As long as you have a floorplan and a power trace,
>> HotSpot should be able to model temperatures for you. No
>> need to change the source code, just configure another
>> .flp file using the file format provided. How to add more
>> than one core into a single silicon is a research
>> question that is not directly related to the HotSPot
>> model. What you suggest is one possible way to do that,
>> but please keep in mind that the max die size is sort of
>> fixed due to the area limit of a reticle, so you might
>> want to shrink the size of each "core" according to CMOS
>> scaling to fit the limited die area.
>>
>>>
>>> 2) How was the power trace file created? I am assuming
>>> that it wasn't done manually?
>>
>> Inside HotSpot release, there is a file, sim-template.c,
>> that shows a template of how to integrated HotSpot with
>> other tools such as SimpleScalar and Wattch. You'll have
>> to implement the details according to you needs.
>>
>>>
>>> 3) I am assuming that Hotfloorplan is not useful in my
>>> scenario because I want to simulate chips that exist,
>>> and hotfloorplan is intended to optimize new designs.
>>> Is that correct?
>>
>> If you just want to assemble several "cores" into on
>> chip, Hotfloorplan might not be useful. However, if you
>> have an idea of what units in your microarchtecture (or
>> cores in your CMP design) and have a rough area
>> estimation for them with some interconnection info among
>> the units, Hotfloorplan will help you find a thermally
>> optimal floorplan with minimum communication delay.
>>
>>>
>>> 4) Does anyone have floorplans for pre-existing chips
>>> that I could see? Even if it is old/dated I would still
>>> like to see how an actual chip is modeled as a Hotspot
>>> floorplan for reference purposes.
>>
>> There is an example floorplan, ev6.flp, which is
>> extracted from Alpha 21364. It should help you to jump
>> start. I am sure there are many chip photographs with
>> dimensions on the Web as well. In the release, there are
>> also many other resources that might be helpful to you,
>> so please be sure to read the READMEs and HOWTOs, and
>> play with the sample files.
>>
>> Hope it helps. Have fun with HotSpot :)
>>
>> -Wei
>>
>>





From ofosho at gatech.edu  Thu Jul 16 13:01:38 2009
From: ofosho at gatech.edu (Omar Chanouha)
Date: Thu, 16 Jul 2009 16:01:38 -0400
Subject: [Hotspot] A Few Questions
In-Reply-To: <DE8D0A45E7D5E90B3CAAEBC9@mstu1>
References: <52EE0C479AFA745AABC28304@mstu1>
	<130f58620907161205i7e20eed8x67e90b4244b94a02@mail.gmail.com>
	<DE8D0A45E7D5E90B3CAAEBC9@mstu1>
Message-ID: <130f58620907161301w5d9f206eq59ea4a7626ba6564@mail.gmail.com>

Thats a shame. Thanks for all the device, I appreciate it. I will get
back to the drawing board.

Thanks,

-O

On Thu, Jul 16, 2009 at 3:23 PM, Wei Huang<wh6p at cms.mail.virginia.edu> wrote:
> Do you mean something like a MCM (multi-chip module in the same package), or
> multiple chip on a PCB with a box? These are currently beyond HotSpot's
> modeling capability. As far as I know, there are no compact models like
> HotSpot at the MCM and box levels. There are commercial tools like FloTherm
> that might be able to model heat transfer and air convection inside a
> computer box using finite element methods, but those might be too slow to
> model chip-level thermal details.
>
> Professor Bianchini's group at Rutgers University has a model called Mercury
> that models the heat transfer by convection among multiple chips/components
> inside something like a box, but they treat each chip as a single node.
> Maybe combining Mercury and HotSpot is a way to approach your needs, but
> that includes non-trivial amount of work.
>
> There is also some work from Professor Zhao Zhang's group at Iowa State on
> processor's thermal impact on DRAM, if I remember correctly. So this might
> also be interesting to you.
>
> -Wei
>
> --On Thursday, July 16, 2009 3:05 PM -0400 Omar Chanouha <ofosho at gatech.edu>
> wrote:
>
>> Thanks for the quick reply Wei. After writing the initial
>> email I realized that it was a little confusing. My idea
>> to add space will not work because as you said it is a
>> way of having multiple cores. I need to be able to
>> simulate multiple chips. Meaning, 2 dies, 2 heatsinks,
>> etc. next to each other. Is this possible? The reason for
>> this is that I would like to see what effect adjacent
>> processors can have on each other during a thermal
>> attack. If it is not currently possible, where would I
>> begin to add this functionality?
>>
>> Thanks,
>>
>> -O
>>
>> On Thu, Jul 16, 2009 at 1:26 PM, Wei
>> Huang<wh6p at cms.mail.virginia.edu> wrote:
>>>
>>> Hi Omar, please see below...
>>>>
>>>> 1) Is there a way to model a floorplan with more than
>>>> one processor using hotspot? If not, could someone help
>>>> me get started changing the source to be able to do
>>>> this? I was thinking that I would build upon existing
>>>> single processor floorplans by doubling the components
>>>> and adding some dead space. Any thoughts on that?
>>>
>>> As long as you have a floorplan and a power trace,
>>> HotSpot should be able to model temperatures for you. No
>>> need to change the source code, just configure another
>>> .flp file using the file format provided. How to add more
>>> than one core into a single silicon is a research
>>> question that is not directly related to the HotSPot
>>> model. What you suggest is one possible way to do that,
>>> but please keep in mind that the max die size is sort of
>>> fixed due to the area limit of a reticle, so you might
>>> want to shrink the size of each "core" according to CMOS
>>> scaling to fit the limited die area.
>>>
>>>>
>>>> 2) How was the power trace file created? I am assuming
>>>> that it wasn't done manually?
>>>
>>> Inside HotSpot release, there is a file, sim-template.c,
>>> that shows a template of how to integrated HotSpot with
>>> other tools such as SimpleScalar and Wattch. You'll have
>>> to implement the details according to you needs.
>>>
>>>>
>>>> 3) I am assuming that Hotfloorplan is not useful in my
>>>> scenario because I want to simulate chips that exist,
>>>> and hotfloorplan is intended to optimize new designs.
>>>> Is that correct?
>>>
>>> If you just want to assemble several "cores" into on
>>> chip, Hotfloorplan might not be useful. However, if you
>>> have an idea of what units in your microarchtecture (or
>>> cores in your CMP design) and have a rough area
>>> estimation for them with some interconnection info among
>>> the units, Hotfloorplan will help you find a thermally
>>> optimal floorplan with minimum communication delay.
>>>
>>>>
>>>> 4) Does anyone have floorplans for pre-existing chips
>>>> that I could see? Even if it is old/dated I would still
>>>> like to see how an actual chip is modeled as a Hotspot
>>>> floorplan for reference purposes.
>>>
>>> There is an example floorplan, ev6.flp, which is
>>> extracted from Alpha 21364. It should help you to jump
>>> start. I am sure there are many chip photographs with
>>> dimensions on the Web as well. In the release, there are
>>> also many other resources that might be helpful to you,
>>> so please be sure to read the READMEs and HOWTOs, and
>>> play with the sample files.
>>>
>>> Hope it helps. Have fun with HotSpot :)
>>>
>>> -Wei
>>>
>>>
>
>
>
>
>

From shervin at ucsd.edu  Thu Jul 23 22:38:39 2009
From: shervin at ucsd.edu (Shervin Sharifi)
Date: Thu, 23 Jul 2009 22:38:39 -0700
Subject: [Hotspot] Flip chip support in Hotspot
Message-ID: <f73279680907232238g3ed4cb9avf1e1ac6dda14c33b@mail.gmail.com>

Hi,
 Is there any support for flip chip in the Hotspot?
 If not, do you have any suggestion to mimic it using the Hotspot?

  Thanks
    Shervin
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From wh6p at cms.mail.virginia.edu  Fri Jul 24 07:09:41 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Fri, 24 Jul 2009 10:09:41 -0400
Subject: [Hotspot] Flip chip support in Hotspot
In-Reply-To: <f73279680907232238g3ed4cb9avf1e1ac6dda14c33b@mail.gmail.com>
References: <f73279680907232238g3ed4cb9avf1e1ac6dda14c33b@ma
 il.gmail.com>
Message-ID: <252388B9F36D16C40D26C3C0@[172.25.179.231]>

Shervin,

The default in HotSpot is flip-chip (i.e. the back of 
silicon substrate is attached to heat spreader and then 
heatsink), since it is the dominant packaging scheme for 
high-performance chips. For wire-bonded chips, the heat 
transfer through the bonding wire is not modeled in 
HotSpot, and the silicon substrate itself is not on the 
primary heat transfer path (transistor layer to heatsink). 
But the error caused by these two factors are usually 
negligible (because bonding wires are long and thin, 
silicon is also very thin). Does this answer your question?

Regards,
Wei

--On Thursday, July 23, 2009 10:38 PM -0700 Shervin Sharifi 
<shervin at ucsd.edu> wrote:

> Hi,
>
>
> ?Is there any support for flip chip in the Hotspot??
> ?If not, do you have any suggestion to mimic it using the
> Hotspot?
> ?
> ??Thanks?
> ?? ?Shervin?
>






From ofosho at gatech.edu  Wed Jul 29 19:43:29 2009
From: ofosho at gatech.edu (Omar Chanouha)
Date: Wed, 29 Jul 2009 22:43:29 -0400
Subject: [Hotspot] Some Very Small Gripes
Message-ID: <130f58620907291943o4e6d3df0t8a50c3fe42e1be81@mail.gmail.com>

Overall my Hotspot experience has been great. There are a couple
things that I think could help out new people in the future.

1. The error message "inordinate floorplan size", means that the
spreader and/or the heatsink size in the .config file are smaller than
the floorplan.

2. The error message "no. of units in floorplan and trace file differ"
is very vague. I went back and had printf dump the actual values. This
lead me to point 3.

3. The last line of the FLP file has to be blank. Without this blank
line Hotspot only recognized the first 35 of 36 entries. If this is
how it should be, that's fine, I just couldn't find any documentation
on the matter.

I am not complaining, I am just trying to prevent another noob from
making the same mistakes.

Great experience otherwise,

-Omar

From wh6p at cms.mail.virginia.edu  Wed Jul 29 20:06:31 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Wed, 29 Jul 2009 23:06:31 -0400
Subject: [Hotspot] Some Very Small Gripes
In-Reply-To: <130f58620907291943o4e6d3df0t8a50c3fe42e1be81@mail.gmail.com>
References: <130f58620907291943o4e6d3df0t8a50c3fe42e1be81@ma
 il.gmail.com>
Message-ID: <71A515402266CDC7D388F6FD@[192.168.5.14]>

Hi Omar,

Glad to know that you like HotSpot and also thank you for 
your suggestions/tips :)

The 2 & 3 points is related to the way your floorplan file 
is edited/generated. If you did it in standard Linux 
editors with newline at the end, it should work (at least 
that is what I found out). However, if you edit the flp 
file in Windows/DOS, the end-of-file causes some 
complications. This compatibility issue of UNIX/Windows is 
common in many other software too. A way to work around it 
in Windows is to copy the end part of the example flp file 
and paste it into your own.

Regards,
Wei

--On Wednesday, July 29, 2009 10:43 PM -0400 Omar Chanouha 
<ofosho at gatech.edu> wrote:

> Overall my Hotspot experience has been great. There are a
> couple things that I think could help out new people in
> the future.
>
> 1. The error message "inordinate floorplan size", means
> that the spreader and/or the heatsink size in the .config
> file are smaller than the floorplan.
>
> 2. The error message "no. of units in floorplan and trace
> file differ" is very vague. I went back and had printf
> dump the actual values. This lead me to point 3.
>
> 3. The last line of the FLP file has to be blank. Without
> this blank line Hotspot only recognized the first 35 of
> 36 entries. If this is how it should be, that's fine, I
> just couldn't find any documentation on the matter.
>
> I am not complaining, I am just trying to prevent another
> noob from making the same mistakes.
>
> Great experience otherwise,
>
> -Omar
> _______________________________________________
> HotSpot mailing list
> HotSpot at mail.cs.virginia.edu
> http://www.cs.virginia.edu/mailman/listinfo/hotspot





From ofosho at gatech.edu  Wed Jul 29 20:08:26 2009
From: ofosho at gatech.edu (Omar Chanouha)
Date: Wed, 29 Jul 2009 23:08:26 -0400
Subject: [Hotspot] Some Very Small Gripes
In-Reply-To: <71A515402266CDC7D388F6FD@192.168.5.14>
References: <130f58620907291943o4e6d3df0t8a50c3fe42e1be81@mail.gmail.com>
	<71A515402266CDC7D388F6FD@192.168.5.14>
Message-ID: <130f58620907292008x3aa0ce66yd241447bf80c215@mail.gmail.com>

I edited it in Kate on a gentoo box. Could be just my set up though.

-Omar

On Wed, Jul 29, 2009 at 11:06 PM, Wei Huang<wh6p at cms.mail.virginia.edu> wrote:
> Hi Omar,
>
> Glad to know that you like HotSpot and also thank you for your
> suggestions/tips :)
>
> The 2 & 3 points is related to the way your floorplan file is
> edited/generated. If you did it in standard Linux editors with newline at
> the end, it should work (at least that is what I found out). However, if you
> edit the flp file in Windows/DOS, the end-of-file causes some complications.
> This compatibility issue of UNIX/Windows is common in many other software
> too. A way to work around it in Windows is to copy the end part of the
> example flp file and paste it into your own.
>
> Regards,
> Wei
>
> --On Wednesday, July 29, 2009 10:43 PM -0400 Omar Chanouha
> <ofosho at gatech.edu> wrote:
>
>> Overall my Hotspot experience has been great. There are a
>> couple things that I think could help out new people in
>> the future.
>>
>> 1. The error message "inordinate floorplan size", means
>> that the spreader and/or the heatsink size in the .config
>> file are smaller than the floorplan.
>>
>> 2. The error message "no. of units in floorplan and trace
>> file differ" is very vague. I went back and had printf
>> dump the actual values. This lead me to point 3.
>>
>> 3. The last line of the FLP file has to be blank. Without
>> this blank line Hotspot only recognized the first 35 of
>> 36 entries. If this is how it should be, that's fine, I
>> just couldn't find any documentation on the matter.
>>
>> I am not complaining, I am just trying to prevent another
>> noob from making the same mistakes.
>>
>> Great experience otherwise,
>>
>> -Omar
>> _______________________________________________
>> HotSpot mailing list
>> HotSpot at mail.cs.virginia.edu
>> http://www.cs.virginia.edu/mailman/listinfo/hotspot
>
>
>
>
>

From skadron at cs.virginia.edu  Thu Jul 30 07:12:47 2009
From: skadron at cs.virginia.edu (Kevin Skadron)
Date: Thu, 30 Jul 2009 10:12:47 -0400
Subject: [Hotspot] Some Very Small Gripes
In-Reply-To: <130f58620907292008x3aa0ce66yd241447bf80c215@mail.gmail.com>
References: <130f58620907291943o4e6d3df0t8a50c3fe42e1be81@mail.gmail.com>	<71A515402266CDC7D388F6FD@192.168.5.14>
	<130f58620907292008x3aa0ce66yd241447bf80c215@mail.gmail.com>
Message-ID: <4A71AA5F.1050102@cs.virginia.edu>

Omar,
Thanks for pointing out these usability issues.  It suggests a couple 
items we should check into and at least add to the FAQ.
/K

Omar Chanouha wrote:
> I edited it in Kate on a gentoo box. Could be just my set up though.
> 
> -Omar
> 
> On Wed, Jul 29, 2009 at 11:06 PM, Wei Huang<wh6p at cms.mail.virginia.edu> wrote:
>> Hi Omar,
>>
>> Glad to know that you like HotSpot and also thank you for your
>> suggestions/tips :)
>>
>> The 2 & 3 points is related to the way your floorplan file is
>> edited/generated. If you did it in standard Linux editors with newline at
>> the end, it should work (at least that is what I found out). However, if you
>> edit the flp file in Windows/DOS, the end-of-file causes some complications.
>> This compatibility issue of UNIX/Windows is common in many other software
>> too. A way to work around it in Windows is to copy the end part of the
>> example flp file and paste it into your own.
>>
>> Regards,
>> Wei
>>
>> --On Wednesday, July 29, 2009 10:43 PM -0400 Omar Chanouha
>> <ofosho at gatech.edu> wrote:
>>
>>> Overall my Hotspot experience has been great. There are a
>>> couple things that I think could help out new people in
>>> the future.
>>>
>>> 1. The error message "inordinate floorplan size", means
>>> that the spreader and/or the heatsink size in the .config
>>> file are smaller than the floorplan.
>>>
>>> 2. The error message "no. of units in floorplan and trace
>>> file differ" is very vague. I went back and had printf
>>> dump the actual values. This lead me to point 3.
>>>
>>> 3. The last line of the FLP file has to be blank. Without
>>> this blank line Hotspot only recognized the first 35 of
>>> 36 entries. If this is how it should be, that's fine, I
>>> just couldn't find any documentation on the matter.
>>>
>>> I am not complaining, I am just trying to prevent another
>>> noob from making the same mistakes.
>>>
>>> Great experience otherwise,
>>>
>>> -Omar
>>> _______________________________________________
>>> HotSpot mailing list
>>> HotSpot at mail.cs.virginia.edu
>>> http://www.cs.virginia.edu/mailman/listinfo/hotspot
>>
>>
>>
>>
> _______________________________________________
> HotSpot mailing list
> HotSpot at mail.cs.virginia.edu
> http://www.cs.virginia.edu/mailman/listinfo/hotspot


From wh6p at cms.mail.virginia.edu  Thu Jul 30 10:26:50 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Thu, 30 Jul 2009 13:26:50 -0400
Subject: [Hotspot] Announcing HotSpot v5.0!
Message-ID: <9FEEE3B62D1625DA603DA047@[10.41.1.239]>

Dear HotSpot Users,

It is our great pleasure to announce a new version of 
HotSpot -- Version 5.0!

Version 5.0 introduces several new features that can be 
useful to your special thermal modeling needs: 1) a 
parameterized heatsink and fan model; 2) secondary heat 
transfer path from silicon to C4 pads to packaging 
substrate to solder ball and printed-circuit board; 3) a 
simple leakage-temperature loop and an interface for users 
to incorporate their own leakage power model.

You can download version 5.0 at the following link:
<http://lava.cs.virginia.edu/HotSpot/download_form2.html>

For more information and more details about HotSpot, please 
visit
<http://lava.cs.virginia.edu/HotSpot/index.htm>

Thank you for your interest in HotSpot!

Regards,
The HotSpot Team

From wh6p at cms.mail.virginia.edu  Thu Jul 30 12:21:02 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Thu, 30 Jul 2009 15:21:02 -0400
Subject: [Hotspot] Convection capacitance
In-Reply-To: <7281f8250907301207j220fa757kf8b7866904981545@mail.gmail.com>
References: <7281f8250907301207j220fa757kf8b7866904981545@ma
 il.gmail.com>
Message-ID: <E67A47C9960BFAEF21A9D7DA@[10.41.1.239]>

Hi Saranya,

It is probably difficult to find thermal capacitance value 
in the package datasheet. But you can estimate it by 
knowing the dimensions of the package, and the material of 
the package (specific heat and density). Usually, the 
thermal cap of package is quite big compared to silicon 
thermal cap, and hence of less interest unless you want to 
know the long-term transient thermal response during the 
warmup phase (tens of seconds to minutes).

Hope this is helpful.

Wei

--On Thursday, July 30, 2009 1:07 PM -0600 saranya 
chandrasekaran <saran86in at gmail.com> wrote:

> Hi,
>
> I'm trying to obtain the temperature values of Xilinx's
> Virtex 4 FPGA using HotSpot, quite similar to the lines
> of this paper
> http://www.cs.virginia.edu/~skadron/Papers/iccd05_siva.pd
> f which uses Virtex 2 Pro. I'm not quite sure what the
> convection capacitance is (I searched the datasheet and
> couldnt get the information) or how it is to be
> calculated for this FPGA device. Can you please help me
> with this query.
>
> Thanks
> Saranya





From supotuco at gmail.com  Thu Jul 30 19:04:33 2009
From: supotuco at gmail.com (diego)
Date: Thu, 30 Jul 2009 22:04:33 -0400
Subject: [Hotspot] (no subject)
Message-ID: <180A85E7-0E1B-46E8-A30D-ED001F6C8624@gmail.com>

what is the format for the power trace files and how do I generate some?

From wh6p at cms.mail.virginia.edu  Fri Jul 31 10:33:47 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Fri, 31 Jul 2009 13:33:47 -0400
Subject: [Hotspot] (no subject)
In-Reply-To: <180A85E7-0E1B-46E8-A30D-ED001F6C8624@gmail.com>
References: <180A85E7-0E1B-46E8-A30D-ED001F6C8624@gmail.com>
Message-ID: <8A9E7B811195840CB177DF98@[172.31.5.173]>

Hi Diego,

There are some sample power trace files (e.g. gcc.ptrace), 
please follow the format therein -- let us know if you have 
problems. As to generating the power trace, you'll have to 
integrate HotSpot with some power simulator (e.g. Wattch). 
We don't have extensive support for that since it is out of 
the scope of HotSpot. However, you may want to take a look 
at sim-template.c, which gives some ideas of how to do the 
integration. Also, there are answers to many other 
questions in the FAQ and HOWTO sections of our website, 
together with the README files within the release.

Hope this is helpful.

Regards,
Wei

--On Thursday, July 30, 2009 10:04 PM -0400 diego 
<supotuco at gmail.com> wrote:

> what is the format for the power trace files and how do I
> generate some?
> _______________________________________________
> HotSpot mailing list
> HotSpot at mail.cs.virginia.edu
> http://www.cs.virginia.edu/mailman/listinfo/hotspot