From wh6p at cms.mail.virginia.edu  Fri Mar  6 08:09:59 2009
From: wh6p at cms.mail.virginia.edu (Wei Huang)
Date: Fri, 06 Mar 2009 11:09:59 -0500
Subject: [Hotspot] [Fwd:  die modeling assumptions]
Message-ID: <18E2092DCB6A7775DC6B9DC0@mstu1>

Hello Nicolas,

Sorry for the long delay. Prof. Skadron forwarded your
email to me a while ago. Please find my answers to your
questions below, just in case Prof. Skadron hadn't done
so...

(I am also cc'ing the HotSpot mailing list in case this is
of general interest to other people.)

> 1/ The die seems to be modeled as a simple silicon
> parallelepiped. Is that right ?

Yes it is. But if you want more accuracy, you can always
divide it vertically into multiple layers and configure
HotSpot to use the grid model.

> 2/ What is approximately the error made on the
> temperature estimation,
> assuming the interconnection layer is negligible ?
> 3/ Why didn't you take this layer into account in the
> Hotspot tool ?

Since the grid model is able to model multiple layers,
interconnect layers can also be included, with some tweaks
by the user. If you are interested in knowing interconnect
temperatures, this is the approach I would recommend.

On the other hand, if you are worrying about neglecting the
impact of the interconnects on silicon temperatures (for
example, lateral heat conduction in those layers or the
self-heating of metal wires), I think those impacts may not
be important for the following reasons:

1) For the interconnect layers to be a source of lateral
heat spreading, we
can argue that since most wires are within blocks, the
lateral heat transfer within those wires will only change
the temperature distribution within that block. For long
wires like buses and clock network, because those wires are
long (consider the length in mm vs. the thickness in um or
less), the lateral thermal resistance of those wires is
huge. Consider an extreme case with a copper sheet of
1mmx1mmx1um, the lateral thermal resistance of that is
2500K/W, whereas the vertical thermal resistance (assuming
the worst thermal case with only dielectrics and no metal)
is about 0.5K/W. So the amount of heat conducted laterally
via the metal layer is really negligible for the global
wires.

2)The self-heating power of interconnect layers eventually
goes through the silicon by heat conduction, so the total
power is already included in the case where only silicon is
assumed to dissipate power.

The only question is whether the self heating of wires is
spatially correlated with the corresponding silicon blocks
underneath. For global wires such as buses and clock
network, this is not the case. But most of the other wires
are pretty much constrained within their own block, so it
is legitimate to count self-heating power in those wires
into their the underlying silicon power. The self-heating
of power supply wires should also be proportional to the
silicon power of the functional block attached to that part
of the power supply grid.

So, my take on this is that for silicon blocks underneath
the global buses and clock network, the silicon temperature
may have some errors. But aren't most of those silicon
areas used for wire buffers or repeaters without  actual
functional units? For other wires, it should pretty
accurate to estimate the silicon power without adding metal
layers (given the secondary  heat transfer path is
negligible).

Hope this answers your concerns. Thanks!

-Wei