From wh6p at virginia.edu Tue Aug 3 15:19:03 2010 From: wh6p at virginia.edu (Wei Huang) Date: Tue, 3 Aug 2010 14:19:03 -0500 Subject: [Hotspot] the effect of vias In-Reply-To: References:

Message-ID: You are right. This is also the way I can think of. Probably start with 1-2 layers of metal for sanity check. Newer technologies use low-k dielectric between metal layers, which has lower thermal conductivity. You might also want to consider that. But starting with SiO2 certainly makes sense. -Wei 2010/8/3 LiYangyang > Thanks a lot Wei. Your suggestion gave me a good idea to do the > estimation of the via effect. > > One problem is, the 'via' I mean the via between different metal layers of > one chip. I notice that the layer stucture that Hotspot uses is: > silicon1, TIM, silicon2, TIM, etc. > I wonder if I only have one silicon or chip, with 6 metal layers, can I > model the structure as: silicon 1--TIM-- metal layers TIM, > or silicon1--TIM--metal layer 1--TIM--metal layer2--TIM--metal layer3, > etc, and the TIMs are SiO2, does this make any sense? > > If the idea makes sense, for the .lcf file, should I use the same floorplan > as used for the silicon layer? > > > > Yangyang > > > > > ------------------------------ > Date: Wed, 28 Jul 2010 17:09:17 -0500 > Subject: Re: [Hotspot] the effect of vias > From: wh6p at virginia.edu > To: wowlyy at hotmail.com > CC: hotspot at mail.cs.virginia.edu > > Hello Yangyang, > > Right now, each layer specified in HotSpot has to be "homogenous", that is, > with the same material. Since vias and surrounding dielectrics are not the > same materials, there is no direct way of knowing the detailed temperature > as per via(s) in HotSpot. > > However, if your intention is to find the average effect, such as "if I add > x% more vias uniformly, how much temperature drop I would get", you can > always use "equivalent" thermal conductivity and specific heat etc. Of > course this is less accurate compared to modeling individual vias, but it > should provide a good estimation. > > We are considering possibilities of supporting multiple materials in one > layer in future releases. > > Hope this helps. > > -Wei > > 2010/7/28 LiYangyang > > Hello Hotspot, > I'm trying to use Hotspot to estimate the effect of adding vias to the > chip temperature, is there any suggestion on how to do this? > Thank you. > > Yangyang Li > > > > _______________________________________________ > HotSpot mailing list > HotSpot at mail.cs.virginia.edu > http://www.cs.virginia.edu/mailman/listinfo/hotspot > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.cs.virginia.edu/pipermail/hotspot/attachments/20100803/58002119/attachment.html From wowlyy at hotmail.com Thu Aug 5 18:00:06 2010 From: wowlyy at hotmail.com (LiYangyang) Date: Fri, 6 Aug 2010 06:00:06 +0800 Subject: [Hotspot] the effect of vias Message-ID: Hi, Wei, it's me again. I do some test of vias using the method we talked last time, with one metal layer. The result seems not as I've expected. There's some possible reasons causing this problem, 1. For the metal layer, the thermal capacitance and specific heat for that layer I uses copper. But in reality, the metal layer is not pure metal. It should be some metal and some SiO2. I don't know how much this will affect the result. 2. I'm not sure if the wires in the metal layer consume power, and I assume they do. So in the power trace file, I deal with the wires as functional blocks , and make up the floor plan and give some random power for each block. \ It's this correct? Should I model the wire(metal) layer as one big block with some power consumption or without power consumption? Thank you. Yangyang Date: Tue, 3 Aug 2010 14:19:03 -0500 Subject: Re: [Hotspot] the effect of vias From: wh6p at virginia.edu To: wowlyy at hotmail.com CC: hotspot at cs.virginia.edu You are right. This is also the way I can think of. Probably start with 1-2 layers of metal for sanity check. Newer technologies use low-k dielectric between metal layers, which has lower thermal conductivity. You might also want to consider that. But starting with SiO2 certainly makes sense. -Wei 2010/8/3 LiYangyang Thanks a lot Wei. Your suggestion gave me a good idea to do the estimation of the via effect. One problem is, the 'via' I mean the via between different metal layers of one chip. I notice that the layer stucture that Hotspot uses is: silicon1, TIM, silicon2, TIM, etc. I wonder if I only have one silicon or chip, with 6 metal layers, can I model the structure as: silicon 1--TIM-- metal layers TIM, or silicon1--TIM--metal layer 1--TIM--metal layer2--TIM--metal layer3, etc, and the TIMs are SiO2, does this make any sense? If the idea makes sense, for the .lcf file, should I use the same floorplan as used for the silicon layer? Yangyang Date: Wed, 28 Jul 2010 17:09:17 -0500 Subject: Re: [Hotspot] the effect of vias From: wh6p at virginia.edu To: wowlyy at hotmail.com CC: hotspot at mail.cs.virginia.edu Hello Yangyang, Right now, each layer specified in HotSpot has to be "homogenous", that is, with the same material. Since vias and surrounding dielectrics are not the same materials, there is no direct way of knowing the detailed temperature as per via(s) in HotSpot. However, if your intention is to find the average effect, such as "if I add x% more vias uniformly, how much temperature drop I would get", you can always use "equivalent" thermal conductivity and specific heat etc. Of course this is less accurate compared to modeling individual vias, but it should provide a good estimation. We are considering possibilities of supporting multiple materials in one layer in future releases. Hope this helps. -Wei 2010/7/28 LiYangyang Hello Hotspot, I'm trying to use Hotspot to estimate the effect of adding vias to the chip temperature, is there any suggestion on how to do this? Thank you. Yangyang Li _______________________________________________ HotSpot mailing list HotSpot at mail.cs.virginia.edu http://www.cs.virginia.edu/mailman/listinfo/hotspot -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.cs.virginia.edu/pipermail/hotspot/attachments/20100806/3998ecef/attachment.html From wh6p at virginia.edu Thu Aug 5 18:29:41 2010 From: wh6p at virginia.edu (Wei Huang) Date: Thu, 5 Aug 2010 17:29:41 -0500 Subject: [Hotspot] the effect of vias In-Reply-To: References: Message-ID: Yangyang, These are all good questions. Please see below... 1. For the metal layer, the thermal capacitance and specific heat for that > layer I uses copper. But in reality, the metal layer is not pure metal. It > should be some metal and some SiO2. I don't know how much this will affect > the result. > certainly should use an equivalent value for a mix of metal and ILD (silicon or low-k dielectric). I guess this would affect the results a lot. > 2. I'm not sure if the wires in the metal layer consume power, and I assume > they do. So in the power trace file, I deal with the wires as functional > blocks , and make up the floor plan and give some random power for each > block. \ > It's this correct? Should I model the wire(metal) layer as one big block > with some power consumption or without power consumption? > The wires does have self-heating power that contributes to the thermal profile, but comparing to silicon power, it is much less. In theory, the silicon power (which is calculated from circuit simulators or architectural power models) should already include the self-heating power, so a more accurate way (in my opinion) would be to estimate the self-heating for metal layers, and subtract that from the silicon power of corresponding blocks. You should also make sure to use proper thickness for metal and ILD layers as well. Hope this helps. -Wei -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.cs.virginia.edu/pipermail/hotspot/attachments/20100805/dfe1b1ad/attachment.html