It might be interesting to look at some of the 486 motherboards.
I recently bought some more cache for a Micronics 486-33, and wrote a quick
& dirty cache buster to see whether I had the jumpering right.
I found that the board uses page mode access to DRAM, so that consecutive
DRAM accesses are barely slower than on-chip-cache accesses. Psuedo-random
accesses spread around bigger than my guess of the page size on 1M DRAM's
show all three levels of the memory hierarchy. However, it is still
competative with a 4D/25 or even other IRIS's on the same dumb benchmark.
The loop of the dumb benchmark is no more than x += n(i), for n an int.
Your "scale" operation looks similar but uses floats. I suppose
the awesomely slow speed of floating point in the *86 would probably more
than compensate for the fast consecutive access to DRAM.
Vernon Schryver, firstname.lastname@example.org
This archive was generated by hypermail 2b29 : Tue Apr 18 2000 - 05:23:02 CDT