On Apr 22, 10:39pm, "John D. McCalpin" wrote:
> Subject: Re: CPU Speed vs. Memory Bandwidth
> In article <C5wvxM.M24@odin.corp.sgi.com> you write:
> >For example, each memory board in a Challenge supports two-eay interleaving:
> >each leaf can start a new read request every 200ns, but the system bus can
deliver request 2X faster. For example, if you had an infinitely fast CPU
Key phrase: -------------------------------------------^^^^^^^^^^^^^^^^^^^
(Current R4400 CPUs are not infinitely fast :-) Thw wording was carefully
chosen!
> latencies) gives the observed 60 MB/s limit.
>
> Is it supposed to be different?
Sounds about right.
As you know:
1) current R4400s have 2-level caches, and relatively little overlap.
2) 150Mhz ones are faster, but not different.
3) TFPs have 1-level caches (as far as FP goes) and more overlap.
4) and T5s will have much more overlap, more prefetching, etc.
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