﻿ CS 3330: Computer Architecture

CS 3330: Past Quizzes

This page does not represent the most current semester of this course; it is present merely as an archive.

These are the questions from the quizzes that have already closed.

Quiz 1:

Convert 0x93 to binary (your answer should consist of exactly 8 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 1.011 in decimal?

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits . What is the exponent? (your answer should consist of exactly 3 characters, each either 0 or 1)

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits. What is the fraction? (your answer should consist of exactly 3 characters, each either 0 or 1)

(Thought question; not part of your grade). Consider a C-style float x that is between 1e-20 and 1e20. Let the low-order bit be called bit 0 and the sign bit bit 31. There is one bit that is guaranteed to be different between x and 4*x; which bit is it? (your answer should be a number between 0 and 31)

Quiz 2:

Convert 0xdad to binary (your answer should consist of exactly 12 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 11.101 in decimal?

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the exponent? (your answer should consist of exactly 4 characters, each either 0 or 1)

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the fraction? (your answer should consist of exactly 5 characters, each either 0 or 1)

(Thought question; not part of your grade). In two's-compliment there is one (and only one) number that is it's own additive inverse (i.e., x = -x). What is that number for 6-bit numbers? (your answer should be exactly 6 characters, each either 0 or 1)

Quiz 3:

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x1f - i for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10

The registers used in the questions have the following initial values:

eax = 0x03020100
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x03020100 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

 True False
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After executing "movl %ecx, (%esp)", which of the following changes?
 A. the contents of memory addresses 5 through 8 B. the contents of memory addresses 8 through 11 C. the contents of memory addresses 9 through 12 D. the contents of memory addresses 12 through 15 E. the contents of register ecx F. the contents of register esp
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After executing "popl %eax", what is the value in register eax?
 A. 0x14151617 B. 0x17161614 C. 0x1718191a D. 0x1a191817
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After executing "pushl %eax", what is the value in register esp?
 A. 4 B. 7 C. 8 D. 9 E. 12
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After executing "pushl %eax", what part of memory now contains 0x03020100?
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Quiz 4:

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x20 + ( * 3)%0xf for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 20 23 26 29 2c 2f 22 25 28 2b 2e 21 24 27 2a 2d

The registers used in the questions have the following initial values:

eax = 0x11223344
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x11223344 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

 True False
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After executing "movl (%esp), %ecx", which of the following changes?
 A. the contents of memory addresses 5 through 8 B. the contents of memory addresses 8 through 11 C. the contents of memory addresses 9 through 12 D. the contents of memory addresses 12 through 15 E. the contents of register ecx F. the contents of register esp
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After executing "popl %eax", what is the value in register eax?
 A. 0x212e2b28 B. 0x2825222f C. 0x282b2e21 D. 0x2f222528
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After executing "popl %eax", what is the value in register esp?
 A. 4 B. 7 C. 8 D. 9 E. 12
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After executing "pushl %eax", what is in memory at byte 8?
 A. 4 B. 8 C. 12 D. 0x11 E. 0x28 F. 0x44
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Quiz 5:

Section 4.2.2 defines the HCL for bit-equality to be

bool eq = (a && b) || (!a && !b);

Section 4.2.3 defines the HCL for word-equality to be

bool Eq = (A == B);

Assume we have two-bit words, so A is made of bits a1 and a0 and B is made of bits b1 and b0. Which of the following defines the bit-level implementation of word-level equality (A == B)?

 A. eq = (a0 == b0) && (a1 == b1); B. eq0 = (a0 && b0) || (!a0 && !b0);  eq1 = (a1 && b1) || (!a1 && !b1); C. eq = ((a0 && b0) || (!a0 && !b0)) && ((a1 && b1) || (!a1 && !b1)); D. eq0 = (a0 == b0); eq1 = (a1 == b1);
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On page 358 we see the following HCL:

int Out4 = [
!s1 && !s0 : A; # 00
!s1        : B; # 01
!s0        : C; # 10
1          : D; # 11
];

The text following this notes "the selection can sometimes be simplified, since only the first matching case is selected. For example, the second expression can be written !s1, rather than the more complicated !s1 && s0, since the only other possibility having s1 equal to 0 was given as the first selection expression." In other words, the above could have been written as

int Out4 = [
!s1 && !s0 : A; # 00
!s1 &&  s0 : B; # 01
s1 && !s0 : C; # 10
s1 &&  s0 : D; # 11
];

without changing its meaning in any way.

Which of the following pieces of C code allow this same kind of flexibility in how we write the boolean expressions?

(Note: more than one of the following options is "correct" and will receive full credit)

 A. if (!s1 && !s0) Out4 = A; else if (!s1)   Out4 = B; else if (!s0)   Out4 = C; else if (1)     Out4 = D; B. if (1)          Out4 = D; if (!s0)        Out4 = C; if (!s1)        Out4 = B; if (!s1 && !s0) Out4 = A; C. Out4 = !s1 && !s2 ? A      : !s1        ? B      : !s0        ? C      :              D; D. if (!s1 && !s0) Out4 = A; if (!s1)        Out4 = B; if (!s0)        Out4 = C; if (1)          Out4 = D;
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Section 4.2.2 defines the HCL for bit-MUX to be

bool out = (s && a) || (!s && b);

Section 4.2.3 defines the HCL for word-MUX to be

int Out = [
s : A;
1 : B;
];

Assume we have two-bit words, so A is made of bits a1 and a0 and B is made of bits b1 and b0. Which of the following defines the bit-level implementation of word-level MUX  ([s: A; 1:B;])?

 A. out0 = (s && a0) || (!s && b0); out1 = (s && a1) || (!s && b1); B. out = ((s && a0) || (!s && b0)) && ((s && a1) || (!s && b1)); C. out0 = (s0 && a0) || (!s0 && b0); out1 = (s1 && a1) || (!s1 && b1); D. out = ((s0 && a0) || (!s0 && b0)) && ((s1 && a1) || (!s1 && b1)); E. out = ((s && a0) || (!s && b0)) || ((s && a1) || (!s && b1)); F. out = ((s0 && a0) || (!s0 && b0)) || ((s1 && a1) || (!s1 && b1));
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Quiz 6:

Assume S is a non-pipelined system and P is a pipelined system. Pipelining increases both throughput and latency. Which of the following cases exemplify these principles? Check all that apply (if any do)
 A. It takes twice as long for P to answer a single sum as it takes S B. It takes twice as long for S to answer a single sum as it takes P C. S can do 150 sums in the same time it takes P to do 100 D. P can do 150 sums in the same time it takes S to do 100

What is meant by "nonuniform partitioning" and why is it a problem?
 A. It means the logic between the registers may vary in size; it is a problem because we have to run the clock slow enough for the biggest block. B. It means the size of the register file between each stage of the pipe varies in size; it is a problem because we have to run the clock slow enough for the biggest register file. C. It means the time needed to compute each operation varies; it is a problem because we have to run the clock slow enough for the slowest operation. D. It refers to the solution to the problem of harmonic oscillations that can occur if every stage of the pipeline is the same size: we make the stages nonuniform to prevent this buildup.
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Diminishing returns means that the more pipeline stages there are, the less benefit we get from adding more stages. Why is this?
 A. The more stages you have, the more non-uniform partitioning matters. B. The throughput doesn't have diminishing returns but once the pipe is deep enough the latency really matters a lot. C. Once the stages get too small we can't meaningfully chop it into smaller pieces anymore. D. As the stages become smaller the delay of the registers between each stage becomes more and more significant.
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Quiz 7:

Compare DRAM and SRAM. Check the true statements from the following:
 A. DRAM is cheaper than SRAM B. DRAM is faster than SRAM C. you have to refresh (read and re-write) DRAM to keep values in it D. you have to refresh (read and re-write) SRAM to keep values in it E. DRAM is more likely to be used for main memory than for on-chip caches F. SRAM is more likely to be used for main memory than for on-chip caches

Suppose a single address sent to the memory module retrieves 128 bits of data. That data is probably retrieved by
 A. a single 128-bit supercell in a memory chip B. combining all of the supercells in a single row of a memory chip C. combining one supercell from each of several memory chips D. none of the above: there's no such thing as a supercell
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It is typical for the I/O Bridge to be connected to three buses: the system bus, the memory bus, and the I/O bus. It routes a signal between pairs of these busses; the figures on pages 569, 570, and 578 show examples of

• System-to-memory (memory write), and

What is an example of memory-to-I/O?

 A. load an image into the graphics adapter B. process a key being pressed C. perform a disk write D. none of the above
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Quiz 8:

Compare DRAM and SRAM. Check the true statements from the following:
 A. DRAM uses more transistors per bit than SRAM B. DRAM uses a capacitor to store a value C. Typically a computer has more DRAM than SRAM

Reading a supercell takes two memory controller operations. In between the two the intermediate data is stored in
 A. a pipeline register B. the memory chip C. the memory controller
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A disk never sends memory to the CPU itself, instead sending it to memory. How does the CPU discover the data is there?

 A. it periodically has the I/O controller ask the memory if it got the data B. it periodically has the I/O controller ask the disk if it sent the data C. the memory has the I/O controller interrupt the CPU when the data arrives D. the disk has the I/O controller interrupt the CPU when the data is sent
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Quiz 9:

One reason that arrays can be faster than linked lists is that their elements are adjacent to one another in memory, where linked list elements may be scattered across widely varying addresses. This is an example of
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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Suppose you have a program that often needs several kilobytes of temporary memory. Re-using the same temporary memory each time can be faster than using different temporary memory each time because of
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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Consider two programs; one runs in a small loop, the other invokes several dozen functions each one. Assuming the amount of work is similar, the loop will almost certainly run faster. At least some of that speed difference is due to
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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"Cache" is pronounced like
 A. cash B. catch C. caysh D. caytch E. cashee F. catchee G. cayshee H. caytchee I. cashay J. catchay K. cayshay L. caytchay
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If we find the data we want in a cache, we call that a
 A. cache find B. cache hit C. cache success
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If we fail to find data in a cache because we have never accessed the data before, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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If we fail to find data in a cache even though we access only a few bytes since we last accessed that same data, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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If we fail to find data in a cache because we've read too much data since we last accessed that same data, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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Quiz 10:

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. If addresses are 32 bits long, how large is the tag stored with each line? Enter your answer as a non-negative integer without leading zeros. ____

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. Ignoring metadata like valid bits and tags, how many bytes of data does the cache store? Enter your answer as a non-negative integer without leading zeros. ____

Suppose a cache can store 64KB of data and is organized with 2-line sets. What is the largest amount of data that cache can serve without encountering a conflict miss?
 A. None B. 32KB C. 64KB D. 128KB E. Unlimited
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Assume that cache F is fully associative and cache D is direct-mapped. Assume the two caches have the same address space and the same total data capacity.
 A. F has fewer tag bits than D B. F has more tag bits than D C. F has the same number of tag bits as D D. You'd need more information to be able to tell which has more tag bits.
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Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Quiz 11:

Loop unrolling is usually used to remove what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Inline substitution (also called "inlining") is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Using multiple accumulators is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Loop blocking is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Adding local variables is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Reassociation of operators is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Which of the following techniques depend on a pipelined processor's ability to work on several instructions at once, and thus would not work in a non-pipelined processor? Check all that apply.
 A. loop unrolling B. inlining C. multiple accumulators D. loop blocking E. local variables F. reassociation

Section 5.2 of the textbook discusses CPE (cycles per element, also called cycles per execution or cycles per instruction in other sources). Their discussion suggests that if I have code with 20 CPE and run it on a problem where my algorithm executes on 100 elements, I should expect the runtime to be:
 A. 0-50 cycles B. 50-220 cycles C. 220-1100 cycles D. 1100-2200 cycles E. more than 2200 cycles
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Quiz 12:

When discussing virtual memory, a single page (check all that apply)
 A. can be in-memory, on-disk, or unallocated B. can be partly in-memory and partly not in-memory C. contains a contiguous block of virtual addresses D. is a fixed-size block of bytes E. is mapped to a contiguous block of physical addresses

From the perspective of a running application, virtual memory looks like
 A. a collection of scattered address pages B. a single flat address space C. nothing; virtual memory is not something application code interacts with
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From the perspective of the operating system, virtual memory looks like
 A. a collection of scattered address pages B. a single flat address space C. nothing; virtual memory is not something the operating system interacts with
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As used by our textbook, a "cached" virtual page is one that is
 A. not (yet) in memory B. partly but not fully in memory C. fully in memory D. fully in memory and at least partly some memory cache E. fully in memory and fully in some memory cache
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What is the difference between "caching" a page, "swapping in" a page, and "paging in" a page? Check all that apply.
 A. caching refers to the cache; the other two refer to memory instead. B. swapping means some memory comes in and some other memory goes out; the other two can refer to something coming in without anything going out. C. paging means moving an entire page of memory; the other two can refer to just parts of a page instead. D. there is no difference; they mean the same thing