Modern processor architectures feature highly complex and sophisticated performance optimizations. However, scaling performance without considering security implications could have serious negative consequences, as evidenced by the recent pile of lawsuits concerning the Meltdown and Spectre microarchitectural attacks. These events have all but highlighted the need to architect systems that can not only run at high speed, but can also exhibit high resilience against security attacks, not just one or the other. The goal of this course is to investigate modern processor architectures for security flaws and further explore novel security-aware designs.
This course is highly research-oriented and entails relevant literature search and in-class brainstorming of ideas and experiments. While our general theme will be hardware security, we will explore topics that span multiple disciplines of computer science, including but not limited to, machine learning (e.g., perceptron predictors, adversarial learning), programming languages (e.g., program analysis, dynamic code instrumentation), and software engineering (e.g., formal verification). Students will work in groups on cross-disciplinary research projects that could potentially lead to top-tier conference publications.
We will use Piazza as our class forum, repository for slides, papers, and project descriptions, and our primary mode of brainstorming outside of class. All general inquiries must be made on Piazza. For group-specific questions or private questions, you can either email me or post a private question on Piazza.
Instructor: Ashish Venkat (email: <lastname>@virginia.edu)
Office Hours: Tu/Th 11am-12pm @ Rice 312 (right after class)
In addition to these, we will also schedule group-specific weekly project meetings. Details to follow in Piazza.
This is a graduate seminar class -- we will be exploring advanced research topics in the areas of computer architecture and security. Third and Fourth year undergraduate students interested to enroll should meet a minimum prerequisite requirement of the undergraduate computer architecture course CS 3300 or equivalent. Graduate students who focus on other complimentary CS disciplines are encouraged to enroll, but are expected to pick up relevant architecture background as we progress through the course. This course will satisfy breadth requirements under the "Computer Systems" category.
The majority of your grade will come from the course project. You will be choosing one out of five research projects that I've identified and will most likely work in groups of 2-3 students (depending upon the class size). I will provide enough background for each of these projects and will meet with each group from time to time, to ensure that you're on track. You are more than welcome to suggest your own topic for the project as long as you convince me of its novelty and relevance. More details will appear on Piazza. Here's the breakdown:
This is an evolving schedule. Will be updated regularly.
| Date | Discussion Topic | Discussion Lead(s) | Due (at 11:59:59 pm) |
|---|---|---|---|
| Aug 28 | Introduction, Motivation, and Course Logistics | Ashish | - |
| Aug 30 | Relevant Background for Course Projects | Ashish | Project Topic Selection |
| Sep 4 | Simultaneous Multithreading | Intel | - |
| Sep 6 | Branch Prediction and Spectre Attacks | Untitled | - |
| Sep 11 | Cache Attacks and Branch Prediction Analysis | Intel/2 | - |
| Sep 13 | Fundamentals of Performance Evaluation | Ashish | Assignment 1 |
| Sep 18 | Fundamentals of Security Evaluation | Ashish | - |
| Sep 20 | Information Leakage in GPUs | Frame Buffer | - |
| Sep 25 | Branchscope and Malware Analysis using Performance Counters | Untitled | - |
| Sep 27 | GPU Side Channel Attacks and Secure GPU Acceleration | Sihang | - |
| Oct 2 | Cache Partitioning and TLB Attacks | Intel/2 | Assignment 2 |
| Oct 4 | Microcode Customization and MCU Reverse Engineering | Rasool | - |
| Oct 9 | Reading Day | ||
| Oct 11 | Contention-Based Covert and Side Channels in Processor Architectures | Intel/2 | - |
| Oct 16 | No Class (Professor on Travel) | ||
| Oct 18 | Turing and Eckert-Mauchly Lectures | David Patterson, John Hennessey, Susan Eggers |
- |
| Oct 23 | No Class (Professor on Travel) | ||
| Oct 25 | Security-Aware Energy Management | Ashish | Assignment 3 |
| Oct 30 | ML-based Online Malware Detection | Untitled | - |
| Nov 1 | Rowhammer Attacks | Frame Buffer | - |
| Nov 6 | NVM Encryption | Sihang | Assignment 4 |
| Nov 8 | SMT Resource Partitioning | Intel/2 | - |
| Nov 13 | Memory Safety and Capability Machines | Rasool | - |
| Nov 15 | Anomaly Detection | Untitled | - |
| Nov 20 | Port Smashing | Intel/2 | - |
| Nov 22 | Thanksgiving Day | ||
| Nov 27 | Project Presentation: IOBleed | Frame Buffer | - |
| Nov 29 | Project Presentation: IQSMASH | Intel/2 | - |
| Dec 4 | Project Presentation: Branch Predictor Hardening | Untitled | - |
| Dec 6 | Project Presentation: Capabilities Under-The-Hood | Rasool | Assignment 5 |
All students at UVA are required to abide by the honor code and pledge to not commit academic fraud. You can discuss, collaborate, and brainstorm ideas both within and outside your group. You're also free to lookup and use source code/tools on the internet with appropriate citations. However, you're not allowed to plagiarize text from another student's assignment or from the internet, and/or falsify data. Cheating will be taken seriously and will be reported to the honor committee.