Solutions to Homework #4 

1)    a)    swap( := op = 7) --> ( R[ra] <-- R[rb]: R[rb] <-- R[ra]):

        b)    Step        RTN
                T0            MA <-- PC: C <-- PC + 4;
                T1            MD <-- M[MA]: PC <-- C;
                T2            IR <-- MD
                T3            MD <-- R[ra];
                T4            C <-- R[rb];
                T5            R[ra] <-- C;
                T6            R[rb] <-- MD;
 

2)   In general, when adding unsigned binary numbers, overflow occurs when the final carry-out is a 1.
      In 2's complement, the final carry-out is always ignored, and overflow occurs when there is a sign change.
      In excess 31, each number x is represented as (x + 31).  Notice that when adding x + y, the result is
      [(x+y)+62].  Thus you need to subtract 31 from the sum.  Then, if you still have overflow, then the sum
      actually resulted in an overflow.
 
 
Unsigned 2's complement Excess 31
a. 100101 (ov) 100101 000110 (ov)
b. 110111 110111 011000
c. 100001 100001 (ov) 000010
d. 011111 (ov) 011111 (ov) 000000 (ov)
e. 000010 (ov) 000010 100011
f. 110000 (ov) 110000 010001 (ov)
g. 110110 110110 010111
h. 100011 (ov) 100011 000100 (ov)
 
 

3)    a)   sign is positive
             exponent e is found by 15 + e = 9, so e is -6
             so the value is 1.01012 * 2-6 which is (1 + 1/4 + 1/16)/64 = 2.05078 * 10-2

        b)    5010 = 1100102  and .7510 = .112
                    so -50.75 = -1.1001011 * 25
                    as in IEEE format, we leave of the leading 1, and the biased exponent value will be 15 + 5 = 2010 = 101002
                    so the answer will be 1 10100 1001011000
 

4)    a) The fetch cycle for the MIPS machine:
 
Time Step Concrete RTN Control Sequence
T0 MA <-- PC : C <-- PC + 1 MAin, PCout, INC, Cin
T1 PC <-- C : MD <-- M[MA] PCin, Cout, MDrd, Read
T2 IR <-- MD IRin, MDout

        b) The pop instruction
 
Time Step Concrete RTN Control Sequence
T3 MA <-- SP : C <-- SP - 1 MAin, SPout, DEC, Cin
T4 MD <-- M[MA] : SP <-- C MDrd, Read, SPin, Cout
T5 MA <-- PC : C <-- PC - 1 MAin, PCout, DEC, Cin
T6 PC <-- C PCin, Cout
T7 C <-- MD Cin, MDout
T8 MD <-- M[MA] MDrd, Read
T9 MA <-- MD MAin, MDout
T10 MD <-- C MDin, Cout
T11 M[MA] <-- MD MDwr, Write, End
 

        c) The add instruction
 
Time Step Concrete RTN Control Sequence
T3 MA <-- SP : C <-- SP - 1 MAin, SPout, Cin, DEC
T4 MD <-- M[MA] : SP <-- C MDrd, Read, Spin, Cout
T5 A <-- MD Ain, MDout
T6 MA <-- SP MAin, SPout
T7 MD <-- M[MA] MDrd, Read
T8 C <-- A + MD Cin, MDout, ADD
T9 MD <-- C MDin, Cout
T10 M[MA] <-- MD MDwr, Write, End
 

    d)
 
 
Time Step Concrete RTN Control Sequence
T3 MA <-- PC : C <-- PC + 1 MAin, Cin, INC, PCout
T4 MD <-- M[MA] : PC <-- C MDrd, Read, PCin, Cout
T5 (Z=1) --> PC <-- MD Z=1 --> (PCin, MDout), End