CFP Bibliography

Updated 12/18/98

B. Childers and J. Davidson, "Architectural Considerations for Application-Specific Counterflow Pipelines", to appear in IEEE 20th Anniversary Conf. on Advanced Research in VLSI, Atlanta, Georgia, March 1999.

B. Childers and J. Davidson, "Application-Specific Pipelines for Exploiting Instruction-Level Parallelism", University of Virginia, Technical Report No. CS-98-14, May 1, 1998.

B. Childers and J. Davidson, "A Design Environment for Counterflow Pipeline Synthesis", Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES '98), during PLDI '98, Montreal, Canada, June 19-20, 1998.

B. Childers and J. Davidson, "A Design Environment for Counterflow Pipeline Synthesis", University of Virginia, Technical Report No. CS-98-05, March 1998.

B. Childers and J. Davidson, "Automatic Counterflow Pipeline Synthesis", University of Virginia, Technical Report No. CS-98-01, January 1998.

B. R. Childers, J. W. Davidson, and W. A. Wulf, "Synthesis of Application-Specific Counterflow pipelines", Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-1), during 2nd Int'l Symp. on High Performance Computer Architecture, San Jose, Ca., February 3-7, 1996.

M. Karthikeyan and S. Nandy, "An Asynchronous Architecture for Digital Signal Processors", Proc. of the European Design and Test Conf., Paris, France, March 17-20, 1998.

P. N. Loewenstein, "Formal Verification of the Counterflow Pipeline Architecture", 1995 Int'l Workshop on Higher Order Logic Theorem Proving and its Applications (HOL95), September 11-14, 1995, Aspen, Colorado. Also available as Lecture Notes in Computer Science, Vol. 971, 1995.

P. G. Lucassen and J. T. Udding, "On the Correctness of the Sproull Conterflow[sic] Pipeline Processor", Second Int'l Symp. on Asynchronous Circuits and Systems, Aizu-Wakamatsu, Japan, March 18-21, 1996.

M. Miller, K. Jank, and S-L Lu, "Nonstalling Counterflow Architecture", Proc. 4th Int'l. Symp. on High-Performance Computer Architecture, pp. 334-341.

K. Jank and S-L Lu, "A Synchronous Implementation of the Counterflow Pipeline Processor", IEEE Int'l. Symp. on Circuits and Systems, Atlanta, Georgia, May 12-15, 1996.

K. Jank, S-L Lu, and M. Miller, "Advances of the Counterflow Pipeline Microarchitecture", Proc. 3rd Int'l Symp. on High-Performance Computer Architecture, pp. 230-236.

M. B. Josephs, P. G. Lucassen, J. T. Udding and T. Verhoeff, "Formal Design of an Asynchronous DSP Counterflow Pipeline: A Case Study in Handshake Algebra", Proc. Int'l Sym. on Advanced Research in Async. Circuits and Systems, pp. 206-215, November 1994.

B. Rahardjo and B. McLeod, "Design and Analysis of a Counterflow Pipeline Processor in SDL", Journal of Microelectronic System Integration, Vol. 4, 1996. Also available as Telecommunications Research Labaoratories Technical Report #95DN11.

A. Severson and B. Nelson, "Throughput in a Counterflow Pipeline Processor", Computer Architecture News, pp. 5-12, Vol. 23, No. 1, March 1995.

R. F. Sproull and I. E. Sutherland and C. E. Molnar, "The Counterflow Pipeline Processor Architecture", IEEE Design and Test of Computers, pp. 48-59, Vol. 11, No. 3, Fall 1994.

T. Werner and V. Akella, "Counterflow Pipeline-Based Dynamic Instruction Scheduling",Second Int'l Symp. on Asynchronous Circuits and Systems, Aizu-Wakamatsu, Japan, March 18-21, 1996.

A. Yakovlev, "Designing Control Logic for Counterflow Pipeline Processors Using Petri Nets", University of New Castle upon Tyne Technical Report #522, 1995.