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CS 551 Lab 4

Lab Objective

In this lab you will investigate the design and implementation of an interrupt service routine for a real time system. This lab is a modification of lab 3. In lab 3 the program used a watchdog timer to react to changes on the track sensors. This can be replaced with an interrupt driven sensor routine. The DIO board can be programmed to generate an interrupt whenever bits on port 0 achieve a programmer specified level. This will allow a user written Interrupt Service Routine (ISR) to execute only when a car passes a sensor. The main objective is to gain a basic understanding of task design and scheduling when using interrupt service routines.

Program Requirements

The program will start cars on both tracks, and will create 3 tasks. Each task will be released by a car activating a specific sensor; Each sensor will trip an interrupt service routine. Some sensors will cause the release of multiple tasks. Each task will have a deadline which is dynamically computed. When multiple tasks are released by the same sensor, the program must determine which task to run first. Tasks will be scheduled using the EDF scheduling algorithm.

Notes on Interrupts and the DIO Board

The DIO Board

The DIO board can be programmed to generate an interrupt based on any of the eight bits on port 0. The interrupts can be programmed to activate on either high (1) or low (0). The interrupts are then interfaced to the VME bus. The VME interrupter works on a Release on Register Access model, so when the port is accessed, the interrupt is reset.

The VME Interrupter

The VME interrupter consists of a series of registers that control the eight I/O interrupt ports and the interrupt mode. The register structure is shown below.

Status/Control Register

The Status/Control Register is mapped to DIOBASE+ $0081, in our case $fbff0081. It has bits for controlling the Green and Red LED's on the front panel, performing software resets (bit 4), and controlling Global interrupt settings. In specific, bit 3 of the register sets and clears the Global Interrupt Enable for the DIO. This is used to turn on and off the ability of the DIO board to generate interrupts.

Interrupt Level Register

The Interrupt Level Register holds the interrupt level issued by the DIO when an interrupt is generated. The level is in the range 1 - 7. The higher the interrupt level, the higher the priority of the interrupt.

Vector Registers

The Interrupt Vector Registers store the vectors for the interrupts generated by the DIO. If the same vector is loaded into each register, the same interrupt routine will be invoked by all interrupts. If unique vectors are loaded into the registers, a different ISR can be invoked by each bit in port 0, this will allow you to design a unique ISR for each sensor. *NOTE: This feature doesn't work for the PowerPC board we are using.

Interrupt Polarity Register

This is used to determine the cause of an interrupt. If a bit is set to 0, an interrupt will be generated on a 1 to 0 transition of the corresponding bit in port 0, if a bit is set to 1, the 0 to 1 transition will trigger an interrupt.

Interrupt Clear Register

This register can be used to clear a specific interrupt, or to test whether an interrupt is pending for a specific bit in port 0.

Interrupt Enable Register

The Interrupt Enable register supports enabling interrupts for each bit in port 0. If the bit in the Enable Register is 0, no interrupts are triggered by the corresponding bit in port 0.

Setting up an ISR

The steps needed to create, load, and use an ISR on the MVME2604

  1. Design and develop the Interrupt Service Routine. There are restrictions on the types of things you can do in an ISR - similar to the restriction on a Watchdog Routine. One aspect to remember is that ISR can be interrupted unless you disable the interrupts while the ISR is running, and enable them when it finishes. (intLock and intUnlock to lock interrupts on the MVME, global interrupt enable bit on the DIO board) Be sure to clear the interrupt point by writing a 1 to the individual bit(s) in the Interrupt Pending/Clear Register.
  2. Use the vxWorks Interrupt Library (intLib) routines to connect the ISR code to the correct vector in the Interrupt Vector table. The Interrupt Vector table on the MVME2604 board supports 7 levels of interrupt. At each location in the IVT, the address of a 'C' routine is stored. When an interrupt is generated, the Routine at the matching level is invoked. For example, if the DIO board is set up to generate a level 5 interrupt when the LAPHIT sensor is tripped, The 2604 will respond by invoking the routine whose address is stored at the vector associated with level 5. To load the address in this location use the vxWorks intConnect(vector,routine, parameter) subroutine. For more details see the vxWorks Reference manual.
  3. Enable interrupts using sysIntEnable.

The steps needed to generate interrupts on the DIO board are:

  1. Write 0 into the Global Interrupt Enable bit in the Status/Control Register ($fbff0081, bit 3) - this will prevent any interrupts from being generated while you are setting the ISR up.
  2. Write the desired interrupt level into the Interrupt Level Register ($fbff0084), The DIO board supports interrupts levels 1 - 7, levels 3 - 6 are reasonable choices.
  3. Write Interrupt Vector (this is the index in the PPC interrupt vector table, where the address of the ISR is located) into the Vector Registers ($fbff0087, 89, 8b, 8d, 8f, 91, 93, 95).
  4. Write the desired pattern to set the interrupt polarity into the Interrupt Polarity Register ($fbff0085). You will probably want to set the interrupt polarity register to 0x00.
  5. Write all 1's into the Interrupt Clear Register, to reset Interrupts ($fbff0080).
  6. Write 1's into the appropriate bits in the Interrupt Enable Register, to enable the individual interrupts ($fbff0083).
  7. Write a 1 into the Global Interrupt Enable bit in the Status/Control Register ($fbff0081, bit 3), this will allow interrupts to be generated in response to changes in port 0.
This code example is to demonstrate how to generate interrupts on the DIO board and respond to them.

Program Specifications (similar to Lab 3)

  • Your program shall create three independent application tasks - Task1, Task2, and Task3.
  • The body of each task shall be a dummy cpu-cycle consuming loop, with loop iterations of N1, N2, and N3, respectively.
  • Task1 shall be invoked when the Test Car crosses sensors LAPHIT, SensorC, SensorE,and SensorG. Upon each invocation, it shall have a dynamically computed deadline equal to the ETA of the Test Car at the next sensor (i.e. If it is invoked for SensorC, the deadline will be the ETA of the Test Car at SensorE).
  • Task2 shall be invoked when the Test Car crosses sensors LAPHIT, and SensorE. Upon each invocation, it shall have a dynamically computed deadline equal to the Current Time + 500ms.
  • Task3 shall be invoked when the Test Car crosses sensor LAPHIT. Upon each invocation, it shall have a dynamically computed deadline equal to the Estimated Completion Time for an entire lap.
  • The program shall use an interrupt service routine to monitor all sensors.
  • Upon a sensor event, the program shall compute the deadlines for all associated tasks, and release them using Earliest Deadline First (EDF) scheduling.

    Steps:

    Pre-Lab Procedure:

  • Design the functionality of the tasks, and determine what data must be shared between them.
  • Design the interrupt service routine needed to respond to sensor events.
  • Design and Implement your code.
  • Record specific problems you encounter in completing the design phase.

    In-Lab Procedure:

    1. Determine the execution time of the dummy loop. Note: This must be done on the rt-target1 system.
    2. Calculate the approximate velocity of the Test Car for the inter-sensor distances.
    3. Choose N1, N2, and N3 to provide a significant execution time for each task. Note: In a real application these tasks would be executing some real, time consuming task.
    4. Analyze the expected behavior of the program under EDF scheduling.
    5. Run the system using the EDF scheduling algorithm. As each task completes, determine if its deadline was met. Print out the deadline success ratio for an entire run. Are all deadlines met?

    Post-Lab Procedure:

    Turn in the following:
  • The design of the tasks.
  • The design of the Interrupt Service Routine.
  • The complete, commented source code, and sample output from your program. Include a path to the online, world readable version of your source code.
  • Discuss problems (especially those specific to developing and testing real time systems) that you experienced in completing this project.

    Writeup Due: April 24

    Author: Jim Gunderson
    Maintained by: Weilin Zhong
    Last modified: Wed April 11 19:51:50 2001