David Tarjan

Contact me at

Resume: [text] [html] (currently offline)

I graduated from the department in June 2009 with a Ph.D in computer engineering.



Publications:

Please note that all publications listed and/or posted here are copyrighted.
Permission is given to make digital or hard copies of all or part of this material without fee for personal
or classroom use, provided that the copies or not made or distributed for profit or commercial advantage,
and that copies bear the appropriate copyright notice and the full bibliographic citation.
To copy otherwise, to republish, etc. requires specific permission and/or a fee.


• Efficient Parallel Merge Sort for Fixed and Variable Length Keys
  A. Davidson, D. Tarjan, M. Garland and J. Owens
  In Proceedings of Innovative Parallel Computing 2012 (InPar), May 2012
  []
  
• A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
  M. Gebhart, D. Johnson, D. Tarjan, S. Keckler, W. Dally, E. Lindholm and K. Skadron
  In ACM Transactions on Computer Systems 30(2): 8 2012, May 2012
  []
  
• Energy-Efficient Mechanisms for Managing Thread Context in Throughput Processors
  M. Gebhart, D. Johnson, D. Tarjan, S. Keckler, W. Dally, E. Lindholm and K. Skadron
  In Proceedings of the 38th International Symposium on Computer Archtitecture 2011 (ISCA), June 2011
  []
  
• The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches
  D. Tarjan and K. Skadron
  In ACM/IEEE Supercomputing Conference 2010 (SC), November 2010
  [preprint]
  
• Federation: Very Low Overhead Out-of-Order Execution
  Michael Boyer, D. Tarjan and K. Skadron
  ACM Transactions on Architecture and Code Optimization (TACO), to appear
  [preprint]
  
• Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance
  Jiayuan Meng, D. Tarjan and K. Skadron
  In Proceedings of the 37th ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2010
  [pdf]
  
• Increasing Memory Miss Tolerance for SIMD Cores
  D. Tarjan, Jiayuan Meng and K. Skadron
  In ACM/IEEE Supercomputing Conference 2009 (SC), November 2009, won best student paper!
  [pdf]
  
• Rodinia: A Benchmark Suite for Heterogeneous Computing
  S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron
  In International Symposium on Workload Characterization (IISWC), October 2009
  [pdf]
  
• Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors
  M. Boyer, D. Tarjan, S. Acton and K. Skadron
  In 23rd IEEE International Parallel and Distributed Processing Symposium, May 2009
  [pdf]
• A Performance Study of General-Purpose Applications on Graphics Processors using CUDA
  S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron
  Journal of Parallel and Distributed Computing, Elsevier, 68(10):1370–1380, 2008.
  [pdf]
• Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
  D. Tarjan, M. Boyer and K. Skadron
  In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008
  [pdf]
• Multithreading vs. Streaming
  D. Tarjan and K. Skadron
  Position Paper in
  Proceedings of the SIGPLAN Workshop on Memory Systems Performance and Correctness, March 2008
  [pdf]
• The Impact of Systematic Process Variations on Symmetrical Performance in Chip Multi-processors
  E. Humenay, D. Tarjan and K. Skadron
  In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, April 2007
  [pdf]
• Impact of Parameter Variations on Multi-Core Chips
  E. Humenay, D. Tarjan and K. Skadron
  In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration,
  in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006
  [pdf]
• Merging path and gshare indexing in perceptron branch prediction
  D. Tarjan and K. Skadron
  ACM Transactions on Architecture and Code Optimization, 2(3), Sep. 2005
  [abstract |pdf |source code]
• An Ahead Pipelined Alloyed Perceptron with Single Cycle Access Time
  D. Tarjan, K. Skadron and M. Stan
  Workshop on Complexity Effective Design (WCED), June 2004.
  [abstract |presentation| pdf]
  
• Temperature-Aware Microarchitecture: Modeling and Implementation
  K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy and D. Tarjan
  ACM Transactions on Architecture and Code Optimization, 1(1), Mar. 2004
  
• Temperature-Aware Computer Systems: Opportunities and Challenges
  K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan
  IEEE Micro, 23(6), Nov-Dec. 2003
• Temperature-Aware Microarchitecture
  K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan
  In Proceedings of the 30th International Symposium on Computer Architecture, San Diego, CA, June 2003
  [abstract|postscript |pdf]
  

Technical Reports:


• Federation: Out-of-Order Execution using Simple In-Order Cores
  D. Tarjan, M. Boyer and K. Skadron
  Univ. of Virginia Dept. of Computer Science Tech. Report CS-2007-11, August 2007
  [pdf]
• CACTI 4.0
  David Tarjan, Shyamkumar Thoziyoor and Norman P. Jouppi
  HP Labs Technical Report HPL-2006-86
  [abstract|pdf]
  
• Merging Path and Gshare Indexing in Perceptron Branch Prediction
  D. Tarjan and K. Skadron
  University of Virginia Dept. of Computer Science Technical Report CS-2004-38, Dec. 2004.
  [abstract| pdf]
  
• Revisiting the Perceptron Predictor Again
  D. Tarjan and K. Skadron
  University of Virginia Dept. of Computer Science Technical Report CS-2004-28, Sept. 2004.
  [abstract| pdf]
  
• Temperature-Aware Microarchitecture: Extended Discussion and Results
  K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan
  University of Virginia Dept. of Computer Science Technical Report CS-2003-08, Apr. 2003.
  [abstract| postscript |pdf]
  
• Simplecalar Simulation: Simulating a Processor with Optical Connection to Main Memory
  D.Tarjan
  Swiss Federal Institute of Technology Zurich Electronics Laboratory Technical Report, Apr. 2002
  [abstract| presentation|gzipped postscript |zipped pdf]
  

Theses:


• Efficient Throughput Cores for Asymmetric Manycore Processors
  David Tarjan
  PhD Thesis, University of Virginia School of Engineering and Applied Sciences, Aug. 2009
  [pdf| presentation]
  
• Merging Path, Global and Local Indexing in Perceptron Branch Prediction
  David Tarjan
  MS Thesis, University of Virginia School of Engineering and Applied Sciences, Jan. 2007
  [pdf| presentation]
  
• Entwicklung einer Simulationsumgebung für hochgradig multimodale Wellenleiterstrukturen
  (Development of a simulation environment for highly multimode waveguides)
  David Tarjan
  Diploma Thesis (equivalent of an MS), Swiss Federal Institute of Technology Zurich, Apr. 2004
  [pdf]
  

  I've posted some notes on how to get your thesis/dissertation correctly formatted and then printed if you're a graduate student in SEAS.

  Last updated: May 2012