My research interests are in the field of computer architecture. The focus areas of my research are:
Resiliency and reliability of processors, the memory hierarchy, and data center infrastructures
Design and evaluation of architectures using non-volatile memory technologies
Energy-efficient design and management of storage systems
Performance, power, and reliability modeling and evaluation methodologies
AMD Innovation Fund Award, 2014
ACM Senior Member, 2011
IEEE Senior Member, 2010
Google Focused Research Award - 2010
Google Faculty Research Award - 2007, 2009
NSF CAREER Award, 2007
Dr. Dobb's Journal,
NSF Highlight to the United States Congress,
Google Research Blog,
M. Qureshi, S. Gurumurthi, B. Rajendran,
Phase Change Memory: From Devices to Systems,
Synthesis Lectures on Computer Architecture,
Morgan and Claypool Publishers, December 2011.
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Memory Errors in Modern Systems: The Good, The Bad, and The Ugly,
Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults,
Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading,
Feng Shui of Supercomputer Memory - Positional Effects in DRAM and SRAM Faults,
Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches,
Intra-Disk Parallelism: An Idea Whose Time Has Come,
(Selected to IEEE Micro Top Picks)
Dynamic Prediction of Architectural Vulnerability From Microarchitectural State,
SlicK: Slice-Based Locality Exploitation for Efficient Redundant Multithreading,
Understanding the Performance-Temperature Interactions in Disk I/O of Server Workloads,
Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management,
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy,
ICR: In-Cache Replication for Enhancing Data Cache Reliability,
DRPM: Dynamic Speed Control for Power Management in Server Class Disks,
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach,
Analyzing Energy Behavior of Spatial Access Methods for Memory-Resident Data,
Program Committee Member
Program Committee Member
Industry Track Program Chair
IEEE Computer Architecture Letters,
Associate Editor (2011-2014); Associate Editor-in-Chief (2010-2011)
NSF Workshop on Cross-Layer Power Optimization and Management,
Invited Participant, February 2012
Sriram Sankar (May 2014)
Dissertation:Impact of Data Center Infrastructure on Server Availability - Characterization, Management and Optimization
MS Thesis:Intra-Disk Parallelism (August 2008)
First Employment: Microsoft, Redmond, WA
Taniya Siddiqua (August 2012)
Dissertation:A Multi-Level Approach to NBTI Mitigation in Processors
Balancing Soft Error Coverage with Lifetime Reliability in Redundantly Multithreaded Processors (September 2009)
First Employment: Intel, Hudson, MA
Clinton Wills Smullen, IV (September 2011)
Dissertation:Designing Giga-Scale Memory Systems with STT-RAM
First Employment: Google, Mountain View, CA
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