Department of Computer Science
University of Virginia
Currently on leave at AMD Research
(Last Updated: April 2014)
||Department of Computer Science
University of Virginia
P.O. Box 400740
Charlottesville, VA 22904-4740
|Department of Computer Science
University of Virginia
85 Engineer's Way
Charlottesville, VA 22904
|| 308 Rice Hall
My research interests are in the field of computer architecture. The focus areas of my research are:
Resiliency and reliability of processors, the memory hierarchy, and data center infrastructures
Design and evaluation of architectures using non-volatile memory technologies
Energy-efficient design and management of storage systems
Performance, power, and reliability modeling and evaluation methodologies
ACM Senior Member, 2011
IEEE Senior Member, 2010
Google Focused Research Award - 2010
Google Faculty Research Award - 2007, 2009
NSF CAREER Award, 2007
Dr. Dobb's Journal,
NSF Highlight to the United States Congress,
Google Research Blog,
M. Qureshi, S. Gurumurthi, B. Rajendran,
Phase Change Memory: From Devices to Systems,
Synthesis Lectures on Computer Architecture,
Morgan and Claypool Publishers, December 2011.
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Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading,
Power Availability Provisioning in Large Data Centers,
GPGPUs: How to Combine High Computational Power with High Reliability,
GPU-Qin: A Methodology for Evaluating the Error Resilience of GPGPU Applications,
Soft Failures in Large Datacenters,
IEEE CAL 2013
Feng Shui of Supercomputer Memory - Positional Effects in DRAM and SRAM Faults,
Datacenter Scale Evaluation of the Impact of Temperature on Hard Disk Drive Failures,
ACM Transactions on Storage 2013
Enhancing NBTI Recovery in SRAM Arrays through Recovery Boosting,
IEEE Transactions on VLSI 2012
The STeTSiMS STT-RAM Simulation and Modeling System,
Delivering on the Promise of Universal Memory for Spin-Transfer Torque RAM (STT-RAM),
Modeling and Analyzing NBTI in the Presence of Process Variation,
Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches,
Industry Session Program Chair
IEEE Computer Architecture Letters,
Associate Editor; Former Associate Editor-in-Chief
Industry Session Program Committee Member
IEEE Micro Top Picks 2014,
Selection Committee Member
Program Committee Member
NSF Workshop on Cross-Layer Power Optimization and Management,
Invited Participant, February 2012
Phase Change Memory Tutorial,
Co-Organizer (Presented HPCA 2010, MICRO 2010, NVMW 2011).
Current Graduate Advisees
MS Thesis:Intra-Disk Parallelism (August 2008)
Taniya Siddiqua (August 2012)
Dissertation:A Multi-Level Approach to NBTI Mitigation in Processors
Balancing Soft Error Coverage with Lifetime Reliability in Redundantly Multithreaded Processors (September 2009)
First Employment: Intel, Hudson, MA
Clinton Wills Smullen, IV (September 2011)
Dissertation:Designing Giga-Scale Memory Systems with STT-RAM
First Employment: Google, Mountain View, CA
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