HPCA 2010 Phase Change Memory Tutorial

Tutorial Duration: Half Day

Abstract

Memory systems consisting of DRAM chips are starting to hit cost and power limits. This has prompted architects to turn to emerging memory technologies to build large capacity, scalable, and power efficient memory systems. Phase Change Memory (PCM) is being viewed as one of the most promising candidates among the emerging technologies and research studies on PCM have started to gain attention in Computer Architecture conferences. Yet, there is little understanding about the fundamental physics and behavioral modeling of PCM in the wider architecture community. The objective of this tutorial is to explain the device level working of phase change memory and provide architectural level abstractions to enable their use for system studies. We will also cover the potential uses of PCM in systems that can leverage the density advantage, power-efficiency, and non-volatility of PCM. PCM has it own unique challenges such as slower read latency (than DRAM), much slower write latency (and write bandwidth), limited write endurance and drift. We will survey existing solutions to these problems and discuss topics for future research.

This tutorial will be presented by researchers from both industry and academia who are actively engaged in PCM research at the device and architecture levels as well as on solid-state disks. The tutorial is intended for both students interested in pursuing system research in emerging memory technologies as well as researchers from industry and academia interested in learning about PCM.

List of topics to be covered

Introduction. Background on emerging technologies. Why PCM?
Device level description of PCM. Strategies for writing to multi-bit PCM cells.
Systems with PCM (hybrid memory, PCM-only main memory) and some key challenges in their realization.
Wear leveling and survey of existing solutions.
Mitigating the performance impact of slow writes.
Solid State Drives: Opportunities & Challenges. How does PCM help?
Summary and discussion of open research topics.

Bio of Organizers/Presenters

Dr. Moinuddin Qureshi is a Research Staff Member at IBM T.J. Watson Research Center. His research interest includes scalable high-performance and power-efficient memory systems. His recent research work includes hybrid memory system using PCM (ISCA’09) and efficient wear leveling for PCM (MICRO’09). He has published more than a dozen papers in architecture conferences and holds three US patents. He received his PhD from the University of Texas at Austin in 2007.

Dr. Sudhanva Gurumurthi is an Assistant Professor in the Computer Science Department at the University of Virginia. Sudhanva's research interests include storage systems and silicon reliability. His contributions to storage systems includes Dynamic RPM drives (ISCA'03), Intra-Disk Parallelism (ISCA'08, IEEE Micro Top Picks'09), and power and temperature modeling of storage systems (ISCA'05, HPCA'06, DAC'07). He is serving or has served on the Program Committees of several top systems conferences including ISCA, ASPLOS, FAST, and SIGMETRICS. He received his BE from the College of Engineering Guindy in 2000 and his PhD from Penn State in 2005 and has held research positions at the IBM Austin Research Lab and Intel Corporation. Sudhanva received the NSF CAREER Award in 2007. He is a member of the ACM and the IEEE.

Dr. Bipin Rajendran is a Research Staff Member at IBM T.J. Watson Research Center. At IBM, he is involved in exploratory research on Phase Change Memory, involving process integration, device modeling and electrical characterization. He has contributed to works that led to the demonstration of the most advanced multi-level demonstration in PCM (Nirschl et al, IEDM '07), universal metrics for reliability characterization of PCM (Rajendran et al, VLSI Technology Symposium '08), analytical model for PCM operation (Rajendran et al, IEDM '08) and PCM data retention models (Y.H Shih et al, IEDM '08). He has published more than 25 papers in peer reviewed journals and conferences, and has been issued 2 US patents. He received a B.Tech degree (in 2000) from Indian Institute of Technology, Kharagpur and M.S (in 2003) and Ph.D (in 2006) from Stanford University.