SRAM, DRAM and rotating magnetic disks have served as the bedrock technologies for designing processor caches, main memory, and storage for many years. However, continued use of these technologies pose several challenges with regard to performance, power, density, and scalability. One way to address these challenges is to use Non-Volatile Memory in lieu of these traditional memory and storage media. Examples of Non-Volatile Memory include Flash, Spin Transfer Torque RAM (STT-RAM), and Phase Change Memory (PCM). While these Non-Volatile Memory offer several benefits such as high density and very low leakage power, they also pose several challenges such as the need for high write currents, slow access times (compared to SRAM and DRAM), and limited endurance.
This project aims to develop a high performance and extremely low-power memory hierarchy for a server, from processor caches down to storage, using Non-Volatile Memory. Additionally, this project also explores how the non-volatility property of these memories can be exploited in interesting ways at the architecture and system levels to enhance performance, energy-efficiency, and dependability. A few contributions of this project to date include relaxed volatility STT-RAM cache designs, Flash endurance enhancement techniques, and the development of architecture design tools for STT-RAM and Flash.
C.W. Smullen, A. Nigam, S. Gurumurthi, M.R. Stan, The STeTSiMS STT-RAM Simulation and Modeling System, International Conference on Computer-Aided Design (ICCAD), November 2011.
A. Nigam, C.W. Smullen, V. Mohan, E. Chen, S. Gurumurthi, M.R. Stan, Delivering on the Promise of Universal Memory for Spin-Transfer Torque RAM (STT-RAM),International Symposium on Low-Power Electronics and Design (ISLPED), August 2011.
C.W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, M.R. Stan, Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches, International Symposium on High Performance Computer Architecture (HPCA), February 2011.
V. Mohan, S. Gurumurthi, M.R. Stan, FlashPower: A Detailed Power Model for NAND Flash Memory, Design Automation and Test in Europe (DATE), March 2010.
V. Mohan, T. Siddiqua, S. Gurumurthi, M.R. Stan, How I Learned to Stop Worrying and Love Flash Endurance, USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage), June 2010.