Technology scaling, which has paved the way for multicore processors, also gives rise to a variety of silicon reliability problems. These problems include particle-induced soft errors and lifetime reliability phenomena, such as Negative Bias Temperature Instability (NBTI) and process variations. These phenomena threaten to break the abstraction that architecture has traditionally provided to the higher layers of the system as a reliable computing substrate. Existing techniques that combat these reliability problems entail significant performance and power overheads. It is imperative to reduce these overheads to effectively harness the computing power of future multicore processors. However, reducing these overheads without seriously compromising the required level of fault protection is challenging.
The goal of this project is to develop fault tolerance techniques that provide
protection against various silicon reliability phenomena while imposing
significantly less performance and power overheads than traditional reliability
techniques. A few contributions of this project include Partial Redundant
Multi-Threading mechanisms, runtime AVF prediction, Recovery Boosting to provide
deep rejuvenation of SRAM cells from NBTI stresses, and combined circuit and
microarchitectural techniques to mitigate NBTI on processor functional units.
T. Siddiqua, S. Gurumurthi, Enhancing NBTI Recovery in SRAM Arrays through Recovery Boosting, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2011.
T. Siddiqua, S. Gurumurthi, A Multi-Level Approach to Reduce the Impact of NBTI on Processor Functional Units, Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
A. Biswas, N. Soundararajan, S.S. Mukherjee, S. Gurumurthi, Quantized AVF: A Means of Capturing Vulnerability Variations over Small Windows of Time, IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2009.
K.R. Walcott, G. Humphreys, S. Gurumurthi, Dynamic Prediction of Architectural Vulnerability From Microarchitectural State, Proceedings of the International Symposium on Computer Architecture (ISCA), pages 516-527, June 2007.
A. Parashar, S. Gurumurthi, A. Sivasubramaniam, SlicK: Slice-Based Locality Exploitation for Efficient Redundant Multithreading, In the Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 95-105, October 2006.