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The International Symposium on Physical Design provides a new and high-quality forum for the exchange of ideas and results in critical areas related to the physical design of VLSI systems. The Symposium is an outgrowth of the ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope includes all aspects of physical design, from interactions with behavior- and logic-level synthesis, to back-end performance analysis and verification.

This year's inaugural Symposium focuses on the challenges of high-performance deep-submicron design, as well as the necessary interactions between physical design and higher-level synthesis tasks. An outstanding slate of technical papers has been selected for oral and poster presentation. These developments are complemented by invited presentations that set forth the contexts and visions for key areas -- process technology, system architecture, circuit design and design methodology -- with an emphasis on their implications for relevant R&D in physical design. The Symposium concludes with a panel of leading experts who each present their unique perspectives as to the critical R&D needs of the field.

0830-0840 Chairs' Welcome

A. B. Kahng and M. Sarrafzadeh

0840-1010 Keynote Address

• Physical Design: Past and Future
  T. C. Hu (UCSD), E. S. Kuh (UCB)

1030-1230 Session 1: Placement and Partitioning

Chairs:

D. Hill (Synopsys)

J. Frankle (Aristo Technology)

• Faster Minimization of Linear Wirelength for Global Placement
  C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet, K. Yan (UCLA, Cadence and IBM)
• Network Flow Based Multi-Way Partitioning with Area and Pin Constraints
  H. Liu, D. F. Wong (UT-Austin)
• Partitioning-Based Standard-Cell Global Placement with An Exact Objective
  D. J. Huang, A. B. Kahng (UCLA and Cadence)
• VLSI/PCB Placement with Obstacles Based on Sequence Pair
  H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)

• The Quarter Micron Challenge: Integrating Physical and Logic Design
  R. Camposano (Synopsys)

Chairs:

R. Camposano (Synopsys)

C. Sechen (Washington)

• Timing Driven Placement in Interaction with Netlist Transformations
  G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
• Regular Layout Generation of Logically Optimized Datapaths
  R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
• Minimizing Interconnect Energy Through Integrated Low-Power Placement and Combinational Logic Synthesis
  G. Holt, A. Tyagi (Iowa State)

1630-1830 Session 3: Contexts (Invited)

• Design Technology Trends Based on NTRS Evolution
  P. Verhofstadt, C. D'Angelo (SRC)
• Microprocessor Architecture, Circuit, and Physical Design Trends
  R. Panwar (Sun)

• Lithography and Dimensional Trends for Future Processes -- Implications for Physical Design
  P. K. Vasudev (Sematech)

Chairs:

T. S. Moh (Silicon Valley Research)

D. F. Wong (UT-Austin)

• On Two-Step Routing for FPGAs
  G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
• A Simple and Effective Greedy Multilayer Router for MCMs
  Y.-J. Cha (Electronic & Telecomm Research Institute), C. S. Rim (Sogang U.), K. Nakajima (Maryland)
• Performance Driven Global Routing for Standard Cells
  J. Cong and P. Madden (UCLA)

1030--1200 Session 5: Steiner Tree Constructions

Chairs:

M. Marek-Sadowska (UCSB)

N. Sherwani (Intel)

• Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving Tree Construction
  J. D. Cho (SungKyunKwan)
• Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design
  J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
• Provably Good Routing Tree Construction with Multi-Port Terminals
  C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)

1330--1500 Session 6: Back-End Design Methodology

Chairs:

C.-K. Cheng (UCSD)

M. Weisel (Intel)

• A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems
  L. Scheffer (Cadence)
• C5M - A Control Logic Layout Synthesis System for High-performance Microprocessors
  J. Burns, J. Feldman (IBM)
• A VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation
  F.-L. Heng, Z. Chen, G. E. Tellez (IBM)

Chairs:

G. Robins (Virginia)

J. D. Cho (SungKyunKwan)

• A Pseudo-Hierarchical Methodology for High Performance Microprocessor Design
  A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo, S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM); T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott, R. Weiss (Cadence)
• Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs
  J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
• Towards a New Benchmarking Paradigm in EDA
  N. Kapur, D. Ghosh, F. Brglez (NCSU)
• How Good are Slicing Floorplans?
  F. Y. Young, D. F. Wong (UT-Austin)
• Slicibility of Rectangular Graphs and Floorplan Optimization
  P. DasGupta, S. Sur-kolay (Indian Institute of Management)
• Power Optimization for FPGA Look-Up Tables
  M. J. Alexander (Washington State)
• A Matrix Synthesis Approach to Thermal Placement
  C. C.-N. Chu, D. F. Wong (UT-Austin)
• Preserving HDL Synthesis Hierarchy for Cell Placement
  Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua)

Authors display and discuss one-on-one the posters presented in Poster Presentation session.

1900--2200 Banquet

Chairs:

W.-M. Dai (UCSC)

L. Jones (Motorola)

• EWA: Exact Wire Sizing Algorithm
  R. Kay, G. Bucheuv, L. Pileggi (CMU)
• Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers
  D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
• Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing
  C. C.-N. Chu, D. F. Wong (UT-Austin)

1030--1230 Session 10: Design Methodology Futures (Invited)

• Chip Hierarchical Design System (CHDS): A foundation for Timing-Driven Physical Design into the 21st Century
  R.G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
• Physical Design 2010: Back to the Future?
  A. R. Newton (UCB)

• Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
  W. J. Grundmann (DEC)

• Physical Design Challenges of Performance
  D. P. LaPotin (IBM Austin Research Lab)
• Panel: Physical Design R&D: What's Missing?

  Moderator: G. Smith (Dataquest)

  W. W.-M. Dai (UCSC)
  E. Hsieh (Avant!)
  M. Hunt (Cadence)
  K. Keutzer (Synopsys)
  D. P. LaPotin (IBM Austin Research Lab)
  N. Sherwani (Intel Hillsboro)