Advance Program 1997 International Symposium on Physical Design Embassy Suites at Napa Valley, Napa, California April 14--16, 1997 http://www.cs.virginia.edu/~ispd97/ The International Symposium on Physical Design provides a new and high-quality forum for the exchange of ideas and results in critical areas related to the physical design of VLSI systems. The Symposium is an outgrowth of the ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope includes all aspects of physical design, from interactions with behavior- and logic-level synthesis, to back-end performance analysis and verification. This year's inaugural Symposium focuses on the challenges of high-performance deep-submicron design, as well as the necessary interactions between physical design and higher-level synthesis tasks. An outstanding slate of technical papers has been selected for oral and poster presentation. These developments are complemented by invited presentations that set forth the contexts and visions for key areas -- process technology, system architecture, circuit design and design methodology -- with an emphasis on their implications for relevant R&D in physical design. The Symposium concludes with a panel of leading experts who each present their unique perspectives as to the critical R&D needs of the field. %%==========================================================================%% %% Monday, April 14 %% %%==========================================================================%% 0830-0840 Chairs' Welcome A. B. Kahng and M. Sarrafzadeh 0840-1010 Keynote Address * Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB) 1010-1030 Break 1030-1230 Session 1: Placement and Partitioning Chairs: D. Hill (Synopsys) J. Frankle (Aristo Technology) * Faster Minimization of Linear Wirelength for Global Placement, C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet, K. Yan (UCLA, Cadence and IBM) * Network Flow Based Multi-Way Partitioning with Area and Pin Constraints, H. Liu, D. F. Wong (UT-Austin) * Partitioning-Based Standard-Cell Global Placement with An Exact Objective, D. J. Huang, A. B. Kahng (UCLA and Cadence) * VLSI/PCB Placement with Obstacles Based on Sequence Pair, H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.) 1230--1430 Lunch (Speaker) * The Quarter Micron Challenge: Integrating Physical and Logic Design R. Camposano (Synopsys) 1430--1600 Session 2: Synthesis and Layout Chairs: R. Camposano (Synopsys) C. Sechen (Washington) * Timing Driven Placement in Interaction with Netlist Transformations, G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich) * Regular Layout Generation of Logically Optimized Datapaths, R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven) * Minimizing Interconnect Energy Through Integrated Low-Power Placement and Combinational Logic Synthesis, G. Holt, A. Tyagi (Iowa State) 1600--1630 Break 1630--1830 Session 3: Contexts (Invited) * Design Technology Trends Based on NTRS Evolution, P. Verhofstadt, C. D'Angelo (SRC) * Microprocessor Architecture, Circuit, and Physical Design Trends, R. Panwar (Sun) 1900--2100 Dinner (Speaker) * Lithography and Dimensional Trends for Future Processes -- Implications for Physical Design P. K. Vasudev (Sematech) %%==========================================================================%% %% Tuesday, April 15 %% %%==========================================================================%% 0830--1000 Session 4: Routing Chairs: T. S. Moh (Silicon valley Research) D. F. Wong (UT-Austin) * On Two-Step Routing for FPGAs, G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto) * A Simple and Effective Greedy Multilayer Router for MCMs, Y.-J. Cha (Electronic & Telecomm Research Institute), C. S. Rim (Sogang U.), K. Nakajima (Maryland) * Performance Driven Global Routing for Standard Cells, J. Cong and P. Madden (UCLA) 1000--1030 Break 1030--1200 Session 5: Steiner Tree Constructions Chairs: M. Marek-Sadowska (UCSB) N. Sherwani (Intel) * Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving Tree Construction, J. D. Cho (SungKyunKwan) * Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design, J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence) * Provably Good Routing Tree Construction with Multi-Port Terminals, C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia) 1200--1330 Lunch 1330--1500 Session 6: Back-End Design Methodology Chairs: C.-K. Cheng (UCSD) M. Weisel (Intel) * A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems, L. Scheffer (Cadence) * C5M - A Control Logic Layout Synthesis System for High-performance Microprocessors, J. Burns, J. Feldman (IBM) * A VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation, F.-L. Heng, Z. Chen, G. E. Tellez (IBM) 1500--1545 Session 7: Poster Presentations Chairs: G. Robins (Virginia) J. D. Cho (SungKyunKwan) * A Pseudo-Hierarchical Methodology for High Performance Microprocessor Design, A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo, S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM); T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott, R. Weiss (Cadence) * Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs, J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State) * Towards a New Benchmarking Paradigm in EDA, N. Kapur, D. Ghosh, F. Brglez (NCSU) * How Good are Slicing Floorplans?, F. Y. Young, D. F. Wong (UT-Austin) * Slicibility of Rectangular Graphs and Floorplan Optimization, P. DasGupta, S. Sur-kolay (Indian Institute of Management) * Power Optimization for FPGA Look-Up Tables, M. J. Alexander (Washington State) * A Matrix Synthesis Approach to Thermal Placement, C. C.-N. Chu, D. F. Wong (UT-Austin) * Preserving HDL Synthesis Hierarchy for Cell Placement Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua) 1545--1715 Session 8: Poster Session Authors display and discuss one-on-one the posters presented in Poster Presentation session. 1900--2200 Banquet %%==========================================================================%% %% Wednesday, April 16 %% %%==========================================================================%% 0830--1000 Session 9: Performance Optimization Chairs: W. W.-M. Dai (UCSC) L. Jones (Motorola) * EWA: Exact Wire Sizing Algorithm, R. Kay, G. Bucheuv, L. Pileggi (CMU) * Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers, D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte) * Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing, C. C.-N. Chu, D. F. Wong (UT-Austin) 1000--1030 Break 1030--1230 Session 10: Design Methodology Futures (Invited) * Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven Physical Design into the 21st Century} R. G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel) * Physical Design 2010: Back to the Future? A. R. Newton (UCB) 1230--1430 Lunch (Speaker) * Physical Design Realities for Digital's StrongARM and Alpha Microprocessors W. J. Grundmann (DEC) 1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited) * Physical Design Challenges of Performance D. P. LaPotin (IBM Austin Research Lab) * Panel: Physical Design R&D: What's Missing? Moderator: G. Smith (Dataquest) W. W.-M. Dai (UCSC) E. Hsieh (Avant!) M. Hunt (Cadence) K. Keutzer (Synopsys) D. P. LaPotin (IBM Austin Research Lab) N. Sherwani (Intel Hillsboro) 1700 Symposium Closes %%==========================================================================%% %% Symposium Organization %% %%==========================================================================%% General Chair: A. B. Kahng (UCLA and Cadence) Past Chair: G. Robins (Virginia) Steering Committee: J. P. Cohoon (Virginia), S. DasGupta (IBM), S.-M. Kang (Illinois), B. Preas (Xerox PARC) Technical Program Chair: M. Sarrafzadeh (Northwestern) Technical Program Committee: C.-K. Cheng (UCSD), W. W.-M. Dai (UCSC), J. Frankle (Aristo Technology), D. D. Hill (Synopsys), J. A. G. Jess (Eindhoven), L. Jones (Motorola), Y.-L. Lin (Tsing Hua), C. L. Liu (Illinois), M. Marek-Sadowska (UCSB), C. Sechen (Washington), K. Takamizawa (NEC), M. Wiesel (Intel), D. F. Wong (UT-Austin), E. Yoffa (IBM) Publicity Chair: M. J. Alexander (Washington State) Local Arrangements Chair: J. Lillis (UCB) Treasurer: S. B. Souvannavong Sponsors: ACM Special Interest Group on Design Automation, in cooperation with IEEE Circuits and Systems Society Additional Support From: Avant! Corporation, Cadence Design Systems, Inc., Intel Corporation, Synopsys Inc., and the U. S. National Science Foundation. %%==========================================================================%% %% Hotel Accommodations and Travel %% %%==========================================================================%% ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service provides daily service between Embassy Suites at Napa Valley and San Francisco International Airport (SFO) approximately every two hours. On Saturdays and Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00, and advance reservations are required. Phone 1-707-255-1559 or FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at: 1075 California Boulevard Napa, CA 94559 Phone: 1-707-253-9540 Fax: 1-707-253-9202 Hotel Reservations: 1-707-253-9540 (ask for the Reservations Dept) 1-800-362-2779 (Central Embassy Suites reservation service.) A block of rooms is being held for the nights of Sunday through Wednesday (April 13 through April 16). Room rates are $105 per night for single or double occupancy. Any individual cancellations within 48 hours from the date of arrival will be billed for (1) night's stay, plus tax. +---------------------------------------------------------+ | Please make room reservations directly with the hotel | | at either 1-707-253-9540 or 1-800-362-2779, mentioning | | ``GROUP CODE ACM''. | +---------------------------------------------------------+ The number of rooms available at this rate is limited, and are only being held through March 21. Early room reservation is highly recommended. For attendees wishing to stay over Friday and Saturday night, a special rate of $129 per night, subject to room availablity, has been arranged for April 11--12 and April 17--19. %%==========================================================================%% %% ISPD-97 Advance Registration Form %% %%==========================================================================%% Name: _______________________________________________________ Company/University: _________________________________________ Responsibility/Title: _______________________________________ Address: ____________________________________________________ City: _______________________________ State: ________________ Country: ______________________ Postal Code: ________________ Phone: ________________________ Fax: ________________________ Email: ______________________________________________________ Food Choices: [ ] Vegetarian meals only [ ] Swordfish or [ ] Filet Mignon (Monday dinner) Advance Late (Through March 17) (After March 17) ACM/IEEE Members [ ] $350 [ ] $425 Non-Members [ ] $425 [ ] $500 Full-Time Students [ ] $175 [ ] $225 Student ID is required if registering as a student. ACM or IEEE Member No. _____________________________ Registration fee includes meals and Banquet. A limited number of additional Banquet tickets are available. _______ Extra Banquet tickets at $50/each. Payment may be submitted via personal or company check in US funds only and drawn on a US bank, made payable to ``ACM/1997 International Symposium on Physical Design''. Payment may also be made with credit card (circle): Mastercard Visa American Express Credit Card # _______________________________________________ Expiration Date: ______________ Total Payment: ______________ Name as it appears on credit card: __________________________ Signature: ___________________________ Date: ________________ Please mail or FAX (credit card only) your completed registration form to: ISPD-97 Symposium Registration Sally Souvannavong, Treasurer P.O. Box 395 Pullman, WA 99163-0395 FAX: 1-509-335-3818 Email registration will not be accepted. Cancellations must be in writing and must be received by March 31, 1997. Questions concerning symposium registration should be directed to Sally Souvannavong at 1-509-334-3162, Email: ispd97@eecs.wsu.edu. %%==========================================================================%% %% Additional Information %% %%==========================================================================%% Check in at Your Convenience: The symposium registration desk will be open from 4pm to 6pm on Sunday, April 13th. On Monday, the registration desk will open at 7:30am and will remain open until 5:00pm. Experience Springtime in Napa Valley: Napa Valley weather is very pleasant in April, with an average high temperature of 78 degrees F and low of 64 degrees F. Attractions include world-famous wineries offering daily tours, golf and outdoor-recreation facilities, and easy access to Marine World--Africa USA. Contact the Napa Valley Tourist Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the following websites for additional information: ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/ Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html Driving Directions from East Bay: Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street exit to California Boulevard (first left turn off freeway). Driving Directions from San Francisco: Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard (first left turn off freeway).