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Napa Valley | Symposium Organization | Information for Authors
Richard Bushroe is a Hewlett-Packard employee on a SEMATECH assignment as ECAD Program Manager to provide leadership and industry development of IC CAE/CAD System/Tool solutions to help close the Design Productivity Gap to meet SEMATECH Member Company requirements for IC designs using 0.25 and 0.18 micron silicon. This has resulted in the development of the Chip Hierarchical Design System (CHDS) and EDA standards (CHDStd). At HP Palo Alto, he was the ICBD Technology Center R&D Lab Manager responsible for IC CAE/CAD System/Tools covering a complete range of CMOS IC design processes. He has spent his career of 28 years in CAE/CAD for Systems, PCB, ASIC, IC. Dick has a BSEE from University of Arizona.
A specialist in behavioral synthesis and embedded system design, Dr. Raul Camposano is Vice President of Engineering for the Design Tools Group of Synopsys. Previously he was General Manager of Design Planning and Director of Design Environment, R&D, at Synopsys since 1993. Prior to joining Synopsys, he concurrently served as the institute director for the German National Research Center for Computer Science (GMD), and professor in the department of computer science at the University of Paderborn, Germany. Between 1986 and 1991, Dr. Camposano led the project on high-level synthesis at the IBM T.J. Watson Research Center. He was also a member of the research staff at the Computer Science Research Laboratory at the University of Karlsruhe.
Dr. Camposano received his B.S.E.E. degree in 1977 and the diploma in electrical engineering in 1978 from the University of Chile, and his Ph.D. in computer science from the University of Karlsruhe in 1981. Active in the EDA professional community, Dr. Camposano serves on various technical program committees and editorial boards worldwide, and has been awarded many accolades and honors for his contributions to the design automation of digital systems.
An active author, Dr. Camposano has written and co-authored three books and a myriad of technical papers on design automation for both academia and industry.
Program Manager, Millenium Project, Sun Microsystems
Biosketch not available at this time
Sumit DasGupta is a Senior Technical Staff Member and Manager of Advanced Physical Design Tools Development at IBM, Austin, TX. Prior to this assignment, he was an IBM assignee to Sematech where he served as a Program Manager for Physical Design and Design for Test. Sumit has a PhD in Computer Science from Syracuse University. He has 7 patents issued and over 15 papers published in external journals and conferences. Sumit is a Senior Member of IEEE and serves in several committees involving IEEE journals and conferences.
William J. Grundmann
William J. Grundmann (Bill) received the B.S.E.E. degree from Oklahoma State University in 1974. He joined Digital Equipment Corporation in 1981 and has been responsible for two generations of microprocessor designs. He has been a major contributor to the implementation of all Digital's microprocessors, associated design methodologies and CAD tools. He is a Senior Consulting Engineer, and the Technical Director of full-custom CAD for Digital Semiconductor. Prior to Digital, he worked in the microprocessor groups of Intel and National Semiconductor.
Edward P. Hsieh
Edward Hsieh is the Director of Product Mangement & Technical Development at Avant! Corporation, Sunnyvale, CA. Prior to joining Avant!, he was a Senior Engineering Manager at IBM Microelectronics in charge of advanced design tools development for deep submicron chip technologies. He was also the Program Manager of the Sematech CHDS (Chip Hierarchical Design system) development project at IBM. Dr. Hsieh received his PhD in Electrical Engineering and Computer Science from Columbia University. Ed has served on several technical program committees including ICCD and MCMC.
T. C. Hu
Dr. T. C. Hu received a B.S. in engineering from National Taiwan
University in 1953, a M.S. in
engineering from the
University of Illinois in 1956, and a Ph.D. in
applied mathematics from
Brown University in 1960.
Presently, he is a Professor of Computer Science and Engineering at
the University of California, San Diego,
in La Jolla, CA.
Dr. Hu is the author of the books Integer Programming and Network Flows (translated into German, Russian, and Japanese) and Combinatorial Algorithms, both published by Addison-Wesley. He is co-editor of Mathematical Programming with S. M. Robinson (Academic Press) and Theory and Concepts of Circuit Layout with E. S. Kuh (IEEE Press), and over eighty technical papers. His current interests are computer-aided design and combinatorial algorithms.
Kurt Keutzer received his B.S. degree in Mathematics from Maharishi International University in 1978 and his M.S. and Ph.D. degrees in Computer Science from Indiana University in 1981 and 1984 respectively.
In 1984 Kurt joined AT&T Bell Laboratories where he worked to apply various computer-science disciplines to practical problems in computer-aided design. In 1991 Kurt joined Synopsys, Inc. where he continues his research as Chief Scientist and Vice-President of Research. Kurt has researched a wide number of areas related to synthesis and high-level design and his research efforts have led to two Design Automation Conference (DAC) Best Paper Awards, a Distinguished Paper Citation from the International Conference on Computer-Aided Design (ICCAD) and a Best Paper Award at the International Conference in Computer Design (ICCD). He co-authored the book entitled Logic Synthesis, published by McGraw-Hill in 1994.
From 1989-1995 Kurt served as an Associate Editor of IEEE Transactions on on Computer-Aided Design of Integrated Circuits and Systems and he currently serves on the editorial boards of three journals: Integration - the VLSI Journal; Design Automation of Embedded Systems and Formal Methods in System Design. Kurt has served on the technical program committees of DAC, ICCAD and ICCD as well as the technical and executive committees of numerous other conferences and workshops.
Ernest S. Kuh
Ernest S. Kuh (Fellow, IEEE) received the B.S. degree from the
Michigan, Ann Arbor, in 1949; the M.S. degree from the
Institute of Technology, Cambridge, in 1950; and the Ph.D. degree from
Stanford University, Stanford, CA in 1952.
He is a Professor of electrical engineering at the University of California, Berkeley. He joined the Electrical Engineering and Computer Science Department faculty in 1956. From 1968 to 1972 he served as Chairman of the department; from 1973 to 1980 he served as Dean of the College of Engineering. From 1952 to 1956 he was a member of the Technical Staff at Bell Telephone Laboratories in Murray Hill, NJ.
David LaPotin received his M.S. degree from Worcester Polytechnic Institute in 1981 and the Ph.D. degree in electrical engineering from Carnegie Mellon University in 1985. From 1978 to 1981 he was a member of the technical staff at GTE Laboratories. In 1985 he joined the IBM T.J. Watson Research Center as a research staff member. He has managed a number of groups in the CAD area and in 1995 moved to Austin, TX to help found the IBM Austin Research Laboratory. He is currently manager of Computer-Aided Design and Analysis.
A. Richard Newton
A. Richard Newton received the B. Eng. and M.Eng.Sci degrees from the University of Melbourne, Australia, in 1973 and 1975 respectively, and the Ph.D. degree from the University of California at Berkeley in 1978. He is currently a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. Since 1979 he has been actively involved as a researcher and teacher in the areas of design technology, electronic system architecture, and integrated circuit design. From 1986-1988 he was Vice Chairman for Computing Resources in the Department of Electrical Engineering and Computer Sciences. Dr. Newton was an Associate Editor of the IEEE Transactions on Computer-Aided Design for Integrated Circuits from 1984-1988 and a member of the Administrative Committee of the IEEE Circuits and Systems Society 1985-1988. Professor Newton has helped with many design technology conferences and workshops over the years and was Technical Program Chair of the 1988 and 1989 ACM/IEEE Design Automation Conferences, Vice Chair of the 1990 Conference and was General Chair of the Conference in 1991. He has received a number of awards for his teaching and research, including Best Paper Awards at the 1988 European Solid State Circuits Conference, the 1987 and 1989 ACM/IEEE Design Automation Conferences, and the International Conference on Computer Design, and he was selected in 1987 as the national recipient of the C. Holmes McDonald Outstanding Young Professor Award of the Eta-Kappa-Nu Engineering Honor Society. In 1989 he was co-recipient of a Best Paper Award for the IEEE Transactions for Computer-Aided Design of Integrated Circuits and Systems. He was a Founding Member of both the EDIF technical and steering committees, an advisor to the CAD Framework Initiative, and was also a Founding Member of EDAC.
In addition to his academic role, Professor Newton has helped to found a number of design technology companies, including SDA Systems (now Cadence Design Systems), PIE Design Systems (now Quickturn), Simplex Solutions, and Synopsys, where he recently rejoined the Board of Directors. He was also a founder and director of nChip, now a part of Flextronics, Inc., Aptix, and Objectivity, and was a director of Interconnectix (now a Mentor Graphics company). Since 1988, he has acted as a Venture Partner with the Mayfield Fund, a high-technology venture capital partnership, where he has contributed to both the evaluation and early-stage development of over a dozen new companies and is presently a Member of the Board of Directors of three of them. From November 1994 to July 1995, Professor Newton was the acting President and CEO of Silicon Light Machines (formerly Echelle, Inc), a development-stage company which is bringing to market a number of display systems based on the application of micromachined silicon light-valves. He is a Member of the ACM and a Fellow of the IEEE.
Naveed Sherwani recieved Ph.D in computer science from University of Nebraska at Lincoln in 1988. His research concentrated on graph theoretic algorithms for routing in printed circuit boards. He joined the Department of Computer Science at Western Michigan University. Naveed's research concentrated on combinatorics, graph algorithms and algorithms for VLSI Physical Design Automation. In particular, Dr. Sherwani concentrated on efficient algorithms for over-the-cell routing to reduce channel routing area. In 1994, Dr. Sherwani joined Intel corporation and currently leads the Strategic CAD Technology group for Physical Design. His work in Intel concentrates on physical design tools and methodologies for layout of microprocessor chips with very high frequency goals.
He has published over seventy five refereed papers in various journal and conferences on these topics. His paper on three layer over-the-cell routing received `distinguished paper' award at ICCAD-91. He has chaired seven conferences and served on technical committees of several others. He is founder of Great Lakes Symposium on VLSI held regularly for the last seven years in the midwest. He is member of the technical committee for ICCAD'97.
Dr. Sherwani has authored or co-authored four books. His book Algorithms for VLSI Physical Design Automation, (Kluwer Academic Press, 1992), now in second edition, is widely used textbook for VLSI Design Automation classes. His work on OTC and three dimensional routing has appeared in book titled Routing in the Third Dimension: From VLSI chips to MCMs. This book is published by IEEE press. Dr. Sherwani has also written an introductory book on multi-chip modules, titled Introduction to Multi-Chip Modules (John Wiley & Sons, 1995). He also the author of new text on graph algorithms, Introduction to Graph Algorithms (in press, to appear in late 1997).
Director and Principal Analyst; Electronic Design Automation Service; Worldwide Online, Multimedia & Software Group.
Mr. Smith is Principal Analyst for Dataquest's Electronic Design Automation (EDA) service of the Software group. He is responsible for all research, publications, and client projects relating to the EDA marketplace. He is also involved in research and consulting projects in the emerging methodologies of RT Level and ES Level Design (ESDA).
Mr. Smith's ongoing activities include the following:
Mr. Smith has more than 25 years of experience in the electronic design market. Starting in the semiconductor industry, he was involved in some of the first attempts at customer-designed ICs. During the 1980s, he specialized in the ASIC end of the semiconductor business. He was instrumental in the development of Plessey's "Megacell" design system, one of the first workstation-based IC design tools. While at IMI, he introduced "EasyGate," a PC-based design system capable of designing 10,000 gate arrays, some of the largest arrays offered at that time. While at LSI Logic Mr. Smith became involved in the development of the RT Level design methodology, later leaving the company to become a consultant in Design Methodology. Mr. Smith joined Dataquest in January 1994.
Mr. Smith received a B.S. degree in Engineering from the United States Naval Academy, Annapolis, Maryland.
Randy Steele is currently the CAD Interconnect Project Manager at SEMATECH - on assignment from Intel Corp. Since joining Intel in 1991, Randy has been Cache Engineering Manager in the Microprocessor Technology Group, and Architect/Senior Designer in the Programmable Logic Products Group. Prior to Intel, Randy was a Design Manager and Senior Designer for various memory and logic groups at SGS-Thomson Microelectronics. Randy graduated from the University of Waterloo in 1985 with a BSEE and has over 20 US patents related to CMOS circuit design and test.
P. K. Vasudev
P. K. Vasudev is currently a Senior Fellow and (acting) Director of Strategic Technology at SEMATECH. His responsibilities include: (1) the development of Long Range Strategic directions ( such as Process/Device/Interconnect Architectures,Design Rules,...etc) for the 0.13um and beyond technology generations and (2) the coordination of Technology Transfer and Commercialization of University/SRC Research programs. Prior to this, he was a Senior Scientist and Program Manager at Hughes Research Laboratories for 14 years working on High Speed CMOS Technology and Circuit design, Optoelectronics and Microwave Devices for RF/Commununication chips. Prior to this he worked for 3 years at Hewlett Packard Research Labs on Low Power CMOS for hand held Product applications. He obtained his PhD and MSEE from Stanford University and his BSEE from Indian Institute of Technology, Kharagpur, India. He holds 20 issued Patents and has published or presented over 100 Technical papers. He is currently a Fellow of the New York Academy of Sciences and the American Advancement of Science (AAAS).