Contact Information:

University of Virginia
Computer Engineering Program
Office: Rice Hall 324
Email: jh3wn[at]virginia[dot]edu
"The supreme happiness in life is the conviction that we are loved."
Research
 home


High power consumption is a major bottleneck for modern IC design. Currently the most effective mechanisms to deal with this issue include Dynamic Voltage & Frequency Scaling (DVFS), power/clock gating, sub-/near-threshold computing. Traditionally, we want to preserve the correctness of computation at all times. As a result, the supply voltage (Vdd) can't be lower than what's required for the critical paths of the circuit to meet their timing constraints. This places a hard limit on the amount of power reduction that can be achieved with those techniques. However, if we think from the perspective of the applications to be implemented, they do not always require correct computation. For example, in multimedia applications, users are unlikely to notice small/rare degradations in the output media quality. In recognition and data mining applications, computation errors often do not affect the final results. In DSP applications, computation error and signal noise can become indistinguishable. For such applications, it is acceptable to relax the correctness requirement and allow circuits to occassionally produce errors. The benefit of introducing errors during computation is improved efficiency metrics (power, area, performance, etc). We denote any circuit construct capable of efficiency-quality tradeoff asImprecise Hardware (IHW).

How do we design IHW? There are in general 3 categories:

1) Voltage overscaling (VOS): Lower the Vdd below what's required of the cirtical paths. Rare but large magnitude errors may occur, but power reduction is significant

2) Structural simplification: Shorten the critical paths of ALUs by breaking their carry-propagate chains with constant 1s and 0s.

3) Algorithmic approximation: Approximating complex math functions with polynomial expansions, less accurate but simpler alternative algorithms in video codec applications, etc.

4) Guardband reduction: scaling the technology-specific timing tables and interconnect resistance & capacitance ratios during a synthesis flow, etc


The focus of my research includes 1) the design and evaluation of arithmetic IHW components 2) the development of a quality-aware energy/power minimization methodology for error-tolerant applications. Here is a list of my publications.