CS 3330: Labs 3-6: Hints for HCL and the simulator

This page does not represent the most current semester of this course; it is present merely as an archive.

You HCL code is basically just routing information around. Any actual work has to be done in other places. This page tries to summarize what you should look for in doing the routing.

seq

For sequential HCL, you have just a few non-HCL components. Three in particular deserve mention:

Register File (Figure 4.28 on page 386)

The seq register file has two read ports A and B and two write ports E and M.

• rA is the A nibble of the register byte of the assembly operation
• srcA is the input that selects which register to read from on port A
• valA is a value that the register file outputs (the value stored in register srcA)
• dstM is the input that selects which register to write to on port M
• valM is the input that selects what value to write on port M

Note that valM and valE are the outputs of memory and ALU, respectively, and there is no HCL in those paths to change that.

The register file is in two phases: reading happens during decode, writing does not actually happen until writeback (after execute and memory).

Memory (Figure 4.30 on page 389)

Memory has only a single port. It takes an address input mem_addr as well as either mem_read, mem_write, or neither. If mem_read is supplied, the output is valM; if mem_write is supplied it has no output but its second input is mem_data.

ALU (Figure 4.29 on page 387)

The ALU and condition codes block takes four inputs:

• alufun, which is what operation to perform
• aluA and aluB, the two operands
• set_cc, whether to set the condition codes or not. Set it for ISA instructions that are math- or logic-centric.

It produces one output you'll need to worry about: valE.

pipe

pipe is messier than seq. The register file, memory, and ALU still behave as with seq but in addition we have a lot more pipeline registers.

Pipeline Register Naming Conventions

A pipeline register sits between two stages of the pipeline. For example, there is a register after decode and before execute.

The outputs of a pipeline register are prefixed by a capital letter corresponding to the following stage: the register after decode and before execute's outputs are prefixed E_.

The signals generated within a phase (including the inputs to the following phase's registers) are prefixed by a lowercase letter corresponding to the phase itself: the signals generated during execute are prefixed e_, including e_dstE which is the input to the register that outputs M_dstE.

As an exception to the above, the bubble/stall inputs to the register set have the same prefix as that register set's outputs: D_bubble is an input to the pipeline register between fetch and decode, for example.

Pipeline Sources and Destinations

(Figure 4.56 on page 426)
The register file reads in the decode stage, so it's signals are prefixed d_: the value d_valA is pulled from register with id d_srcA.

(Figure 4.56 on page 426)
The register file writes in the writeback stage, so it's signals are prefixed w_: the value w_valE is written to the register w_dstE. Note that Figure 4.56 labels them W_ not w_ because the hcl sets them equal to eachother with lines like int w_dstM = W_dstM;

(Figure 4.59 on page 431)
The memory read/write happens in the memory phase, but it's signals are not specially prefixed because mem_addr and mem_data only appear in that one phase. It's output is called m_valM.