CS 3330: Past Quizzes

Convert 0x93 to binary (your answer should consist of exactly 8 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 1.011 in decimal?

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits . What is the exponent? (your answer should consist of exactly 3 characters, each either 0 or 1)

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits. What is the fraction? (your answer should consist of exactly 3 characters, each either 0 or 1)

(Thought question; not part of your grade). Consider a C-style float x that is between 1e-20 and 1e20. Let the low-order bit be called bit 0 and the sign bit bit 31. There is one bit that is guaranteed to be different between x and 4*x; which bit is it? (your answer should be a number between 0 and 31)

Convert 0xdad to binary (your answer should consist of exactly 12 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 11.101 in decimal?

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the exponent? (your answer should consist of exactly 4 characters, each either 0 or 1)

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the fraction? (your answer should consist of exactly 5 characters, each either 0 or 1)

(Thought question; not part of your grade). In two's-compliment there is one (and only one) number that is it's own additive inverse (i.e., x = -x). What is that number for 6-bit numbers? (your answer should be exactly 6 characters, each either 0 or 1)

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x1f - i for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10

The registers used in the questions have the following initial values:

eax = 0x03020100
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x03020100 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

True False

Reset Selection

After executing "movl %ecx, (%esp)", which of the following changes? Reset Selection

After executing "popl %eax", what is the value in register eax? Reset Selection

After executing "pushl %eax", what is the value in register esp? Reset Selection

After executing "pushl %eax", what part of memory now contains 0x03020100? Reset Selection

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x20 + (i  * 3)%0xf for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 20 23 26 29 2c 2f 22 25 28 2b 2e 21 24 27 2a 2d

The registers used in the questions have the following initial values:

eax = 0x11223344
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x11223344 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

True False

Reset Selection

After executing "movl (%esp), %ecx", which of the following changes? Reset Selection

After executing "popl %eax", what is the value in register eax? Reset Selection

After executing "popl %eax", what is the value in register esp? Reset Selection

After executing "pushl %eax", what is in memory at byte 8? Reset Selection

Section 4.2.2 defines the HCL for bit-equality to be

    bool eq = (a && b) || (!a && !b);

Section 4.2.3 defines the HCL for word-equality to be

    bool Eq = (A == B);

Assume we have two-bit words, so A is made of bits a₁ and a₀ and B is made of bits b₁ and b₀. Which of the following defines the bit-level implementation of word-level equality (A == B)?

Reset Selection

On page 358 we see the following HCL:

int Out4 = [
        !s1 && !s0 : A; # 00
        !s1        : B; # 01
        !s0        : C; # 10
        1          : D; # 11
];
 

The text following this notes "the selection can sometimes be simplified, since only the first matching case is selected. For example, the second expression can be written !s1, rather than the more complicated !s1 && s0, since the only other possibility having s1 equal to 0 was given as the first selection expression." In other words, the above could have been written as

int Out4 = [
        !s1 && !s0 : A; # 00
        !s1 &&  s0 : B; # 01
         s1 && !s0 : C; # 10
         s1 &&  s0 : D; # 11
];

without changing its meaning in any way.

Which of the following pieces of C code allow this same kind of flexibility in how we write the boolean expressions?

(Note: more than one of the following options is "correct" and will receive full credit)

Reset Selection

Section 4.2.2 defines the HCL for bit-MUX to be

    bool out = (s && a) || (!s && b);

Section 4.2.3 defines the HCL for word-MUX to be

    int Out = [
      s : A;
      1 : B;
    ];

Assume we have two-bit words, so A is made of bits a₁ and a₀ and B is made of bits b₁ and b₀. Which of the following defines the bit-level implementation of word-level MUX  ([s: A; 1:B;])?

Reset Selection

Assume S is a non-pipelined system and P is a pipelined system. Pipelining increases both throughput and latency. Which of the following cases exemplify these principles? Check all that apply (if any do)

	A.	It takes twice as long for P to answer a single sum as it takes S
	B.	It takes twice as long for S to answer a single sum as it takes P
	C.	S can do 150 sums in the same time it takes P to do 100
	D.	P can do 150 sums in the same time it takes S to do 100

What is meant by "nonuniform partitioning" and why is it a problem? Reset Selection

Diminishing returns means that the more pipeline stages there are, the less benefit we get from adding more stages. Why is this? Reset Selection

Compare DRAM and SRAM. Check the true statements from the following:

	A.	DRAM is cheaper than SRAM
	B.	DRAM is faster than SRAM
	C.	you have to refresh (read and re-write) DRAM to keep values in it
	D.	you have to refresh (read and re-write) SRAM to keep values in it
	E.	DRAM is more likely to be used for main memory than for on-chip caches
	F.	SRAM is more likely to be used for main memory than for on-chip caches

Suppose a single address sent to the memory module retrieves 128 bits of data. That data is probably retrieved by Reset Selection

It is typical for the I/O Bridge to be connected to three buses: the system bus, the memory bus, and the I/O bus. It routes a signal between pairs of these busses; the figures on pages 569, 570, and 578 show examples of

• System-to-I/O (request disk read)
• I/O-to-memory (perform disk read)
• System-to-memory (memory write), and
• Memory-to-system (memory read)

What is an example of memory-to-I/O?

Reset Selection

Compare DRAM and SRAM. Check the true statements from the following:

	A.	DRAM uses more transistors per bit than SRAM
	B.	DRAM uses a capacitor to store a value
	C.	Typically a computer has more DRAM than SRAM

Reading a supercell takes two memory controller operations. In between the two the intermediate data is stored in Reset Selection

A disk never sends memory to the CPU itself, instead sending it to memory. How does the CPU discover the data is there?

Reset Selection

One reason that arrays can be faster than linked lists is that their elements are adjacent to one another in memory, where linked list elements may be scattered across widely varying addresses. This is an example of Reset Selection

Suppose you have a program that often needs several kilobytes of temporary memory. Re-using the same temporary memory each time can be faster than using different temporary memory each time because of Reset Selection

Consider two programs; one runs in a small loop, the other invokes several dozen functions each one. Assuming the amount of work is similar, the loop will almost certainly run faster. At least some of that speed difference is due to Reset Selection

"Cache" is pronounced like Reset Selection

If we find the data we want in a cache, we call that a Reset Selection

If we fail to find data in a cache because we have never accessed the data before, we call that a Reset Selection

If we fail to find data in a cache even though we access only a few bytes since we last accessed that same data, we call that a Reset Selection

If we fail to find data in a cache because we've read too much data since we last accessed that same data, we call that a Reset Selection

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. If addresses are 32 bits long, how large is the tag stored with each line? Enter your answer as a non-negative integer without leading zeros. ____

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. Ignoring metadata like valid bits and tags, how many bytes of data does the cache store? Enter your answer as a non-negative integer without leading zeros. ____

Suppose a cache can store 64KB of data and is organized with 2-line sets. What is the largest amount of data that cache can serve without encountering a conflict miss? Reset Selection

Assume that cache F is fully associative and cache D is direct-mapped. Assume the two caches have the same address space and the same total data capacity. Reset Selection

Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time. Reset Selection

Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time. Reset Selection

Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time. Reset Selection

Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time. Reset Selection

Loop unrolling is usually used to remove what source of inefficiency? Reset Selection

Inline substitution (also called "inlining") is usually used to reduce what source of inefficiency? Reset Selection

Using multiple accumulators is usually used to reduce what source of inefficiency? Reset Selection

Loop blocking is usually used to reduce what source of inefficiency? Reset Selection

Adding local variables is usually used to reduce what source of inefficiency? Reset Selection

Reassociation of operators is usually used to reduce what source of inefficiency? Reset Selection

Which of the following techniques depend on a pipelined processor's ability to work on several instructions at once, and thus would not work in a non-pipelined processor? Check all that apply.

	A.	loop unrolling
	B.	inlining
	C.	multiple accumulators
	D.	loop blocking
	E.	local variables
	F.	reassociation

Section 5.2 of the textbook discusses CPE (cycles per element, also called cycles per execution or cycles per instruction in other sources). Their discussion suggests that if I have code with 20 CPE and run it on a problem where my algorithm executes on 100 elements, I should expect the runtime to be: Reset Selection

When discussing virtual memory, a single page (check all that apply)

	A.	can be in-memory, on-disk, or unallocated
	B.	can be partly in-memory and partly not in-memory
	C.	contains a contiguous block of virtual addresses
	D.	is a fixed-size block of bytes
	E.	is mapped to a contiguous block of physical addresses

From the perspective of a running application, virtual memory looks like Reset Selection

From the perspective of the operating system, virtual memory looks like Reset Selection

As used by our textbook, a "cached" virtual page is one that is Reset Selection

What is the difference between "caching" a page, "swapping in" a page, and "paging in" a page? Check all that apply.

	A.	caching refers to the cache; the other two refer to memory instead.
	B.	swapping means some memory comes in and some other memory goes out; the other two can refer to something coming in without anything going out.
	C.	paging means moving an entire page of memory; the other two can refer to just parts of a page instead.
	D.	there is no difference; they mean the same thing

A page table is Reset Selection

A translation lookaside buffer (TLB) is Reset Selection

For a multi-level page table, the first level page table(s) of process P Reset Selection

For a multi-level page table, the second level page table(s) of process P Reset Selection

Core i7 memory uses four virtual page numbers because it's MMU has a four-level page table hierarchy. Consider translating a single virtual address into a physical address. Which following numbers of page table accesses could occur during that translation? If different states of the caches and so on could result in different numbers of page table lookups, check multiple answers.

	A.	0
	B.	1
	C.	2 or 3
	D.	4
	E.	5 or more

When the CPU is interrupted, how does it know which device created the interruption? Reset Selection

What distinguishes a fault from a trap? Check all that apply

	A.	A trapping instruction does not get re-run after the trap is handled, but a faulting instruction does get re-run after the fault is handled
	B.	A trapping instruction always creates an exception, but a faulting exception only sometimes creates an exception
	C.	Traps are used primarily to talk to the operating system, faults are used primarily to recover from errors
	D.	Traps are handled by the OS, faults are not
	E.	Traps are not handled by the OS, faults are

The assembly instruction "int x" used to make system calls only accepts a 1-byte (256-value) argument x, but Linux uses it to support over 300 system calls. How does it do that? Reset Selection

In hardware, everything runs in parallel unless data dependencies prevent that

A. True B. False

Reset Selection

In software, everything runs in parallel unless data dependencies prevent that

A. True B. False

Reset Selection

The hardware is aware of the program stack

A. True B. False

Reset Selection

Put the following (listed in alphabetical order) in order of importance when optimizing code that operates on very large arrays: B = Body of loop optimization (function inlining, efficient math), C = Cache locality, O = big-O of algorithm used. Answer as three capital letters, no spaces, such as BCO

How does knowing you have a pipelined processor change the code you write? Reset Selection

The operating system is involved when there is a cache miss

A. True B. False

Reset Selection

The operating system is involved when there is a page fault

A. True B. False

Reset Selection

: Which two of the following four binary number formats are used by modern computer hardware?

	A.	one's-complement integer
	B.	sign-magnitude integer
	C.	two's-complement integer
	D.	unsigned integer

: Binary 0011 + binary 1001 = ____ (answer in binary with exactly four characters, each either 0 or 1)

: 0x3f ^ 0x15 = ____ (answer in lower-case hexidecimal with exactly two characters, each between 0 and f)

: Which of the following is true for all possible values of unsigned x? Reset Selection

If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, which of the following numbers (shown in binary) is the largest finite number it can represent? Reset Selection

If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, what is the smallest positive number (> 0) it can represent? Answers are shown in binary Reset Selection

Consider the following eight binary C operators: + - * / % ^ & |. Consider the 32 bits representing the result of "x operator y", where x and y are each either int or unsigned int. For how many of these 8 operators will those bits differ depending on the singed/unsigned nature of x and y? Your answer should be a single digit between 0 and 8:

How many total bytes of data can be stored in the (integer) IA32 program registers at one time? (a program register is one you can use as an operand when in programming in IA32 assembly) Reset Selection

The textbook uses ATT-format assembly, the default for most GNU tools. Some other tools use Intel-format assembly instead. Each of the following is true for only one of the two formats. Check those that are true of ATT-format assembly:

	A.	there is a separate opcode for adding 32-bit values (addl) and 16-bit values (addw)
	B.	register names are preceded by a percent-sign (e.g. %eax)
	C.	memory addresses are written with square brackets and math operators (e.g. [edx+4])
	D.	add A B (where A and B are registers) stores the sum of A and B into register A
	E.	sub A B (where A and B are registers) evaluates B - A, not A - B

"pushl %eax;" is the same as Reset Selection

The "imul" instruction has only one operand, as in "imul $101;", but the multiplication operation is implements requires two operands. The second operand is Reset Selection

In Java, C++, etc, there are types: a String is not the same as a Scanner, and so on. Types are distinct from "meaning": int x might *mean* your age and int y might *mean* your number of siblings, but the language doesn't stop you from saying "x = y" because they are both *type* int. In assembly Reset Selection

IA32 (also called x86) is CISC, not RISC, because (check all that apply)

	A.	each instruction takes the same time to execute
	B.	it has a lot of instructions or opcodes
	C.	math operations can only operate with register operands (not memory)
	D.	some instructions are encoded in just a single byte while others are much longer
	E.	some instructions provide high-level abstractions, hiding lots of action under the hood
	F.	there are many program registers

Two of the following are equivalent to the single-bit mux that the book denotes [ s : A; 1 : B; ], the other two are not equivalent to that mux. Mark the two that are:

	A.	(s == A) || (s ^ B)
	B.	(s == (A && B)) || (s != (A || B))
	C.	s ? A : B
	D.	(s && A) || (!s && B)

Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware retrieve the value stored in register %edx? Reset Selection

Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware decide where the result will be stored? Reset Selection

Not all stages are invovled in executing all instructions. Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. Which (if any) stages are not involved in handling this instruction? Check any that apply

	A.	Fetch
	B.	Decode
	C.	Execute
	D.	Memory
	E.	Writeback

Which of the following operations read a value from memory? Check all that apply

	A.	nop
	B.	rrmovl
	C.	irmovl
	D.	rmmovl
	E.	mrmovl
	F.	OPl
	G.	jXX
	H.	call
	I.	ret
	J.	pushl
	K.	popl

Which of the following operations write a value to memory? Check all that apply

	A.	nop
	B.	rrmovl
	C.	irmovl
	D.	rmmovl
	E.	mrmovl
	F.	OPl
	G.	jXX
	H.	call
	I.	ret
	J.	pushl
	K.	popl

Which of the following operations write a value to a program register? Check all that apply

	A.	nop
	B.	rrmovl
	C.	irmovl
	D.	rmmovl
	E.	mrmovl
	F.	OPl
	G.	jXX
	H.	call
	I.	ret
	J.	pushl
	K.	popl

Which of the following operations read a value from a program register? Check all that apply

	A.	nop
	B.	rrmovl
	C.	irmovl
	D.	rmmovl
	E.	mrmovl
	F.	OPl
	G.	jXX
	H.	call
	I.	ret
	J.	pushl
	K.	popl

The book discusses using the ALU just to forward values for some operations (e.g., their irmovl has the ALU compute 0 + valC) and to do math for other operations. The forwarding is just a design choice and could have been done otherwise, but the math is intrinsic to the operation of Y86. Which of the following operations use the ALU to do math?

	A.	nop
	B.	rrmovl
	C.	irmovl
	D.	rmmovl
	E.	mrmovl
	F.	OPl
	G.	jXX
	H.	call
	I.	ret
	J.	pushl
	K.	popl

When building a chip, we can pick any clock speed we want; the goal is to make it as fast as we can while still being slow enough that no register grabs onto a value before that value has stabilized. Which of the following instructions would be most likely to determine the SEQ clock speed? Reset Selection

In general, pipelining Reset Selection

Nonuniform partitioning happens when Reset Selection

Suppose instruction A is followed by instruction B in the assembled code. There is a hazard between A and B if (check all that apply)

	A.	A's inputs depend on B's outputs
	B.	B's inputs depend on A's outputs
	C.	Whether A runs depends on the outcome of B
	D.	Whether B runs depends on the outcome of A

In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "stall" signal? Reset Selection

In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "bubble" signal? Reset Selection

Which of the following is orders from slowest to fastest? Reset Selection

Data can be stored in program registers, memory, or disk. Which of the following technologies (if any) is/are most commonly associated with memory? Check all that apply

	A.	D Flip-flops
	B.	DRAM
	C.	Ethernet
	D.	Magnetic disk
	E.	Solid-state disk
	F.	SRAM

Which of the following needs to be read and then re-written periodically in order to retain its storage? Check all that apply

	A.	DRAM
	B.	Magnetic disk
	C.	Solid-state disk
	D.	SRAM

Which of the following needs power in order to retain its storage? Check all that apply

	A.	DRAM
	B.	Magnetic disk
	C.	Solid-state disk
	D.	SRAM

Code has good spatial locality if Reset Selection

Code has good temporal locality if Reset Selection

Which of the following describes the kind of caching that the memory hierarchy implements? Reset Selection

Section 6.4 talks about blocks, caches, lines, and sets. Which one is contained by which other? Answer with four capital letters (B, C, L, and S) concatenated from outermost-to-innermost; for example, if believe that blocks contain caches which contain lines which contain sets, your answer should be BCLS

In a set-associative cache, which of the following can be determined from the memory address and cache organization alone (i.e., without knowing the cache contents)? Check all that apply.

	A.	block offset
	B.	set index
	C.	tag
	D.	which byte in the cache to access
	E.	which line in the cache to access
	F.	which set in the cache to access
	G.	valid bit

Which of the following is expected to run fastest? Assume N and M are large numbers. Reset Selection

Which of the following is expected to run fastest? Assume N is a large number. Reset Selection

Which of the following are *not* tips for optimizing memory accesses given in the textbook? Check all that apply

	A.	focus on the common case
	B.	focus on inner loops
	C.	get in the habit of performing cache optimizations everywhere
	D.	reduce cache misses even if it means a few more memory accesses
	E.	try to read memory in sequential order
	F.	try to use data as often as possible once it has been read into memory

We want to loop over all i, j, and k (between 0 and 10240) and run the following: a[i][j] = b[i][k] * c[k][j] In order to maximize cache locality, in what order should the loops be placed? Reset Selection

Which of the following is describes the situations in which you should optimize your code for cache locality? Reset Selection

Using a #define IDX (like those shown in class) and a 1D array instead of a 2D array is done because Reset Selection

Suppose function A is O(n) and for n=1 takes 100ms; function B is O(n^2) and for n=1 takes 1ms. Which of the following n do you expect to be the smallest for which A is faster than B? Reset Selection

Register spilling is when Reset Selection

Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations). Reset Selection

Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations). Reset Selection

If a virtual page is allocated and in physical memory, how do we discover the physical page number? Reset Selection

If a virtual page is allocated but is not in physical memory, how do we discover the physical page number? Reset Selection

If a virtual page is not allocated, how do we discover the physical page number? Reset Selection

Page tables are stored in Reset Selection

If you have a single-level page table, the amount of space it requires varies based on how many pages are in use.

A. True B. False

Reset Selection

If you have a multi-level page table, the amount of space it requires varies based on how many pages are in use.

A. True B. False

Reset Selection

If your program uses 100% of the virtual address space (even the parts normally not used), having a multi-level page table requires Reset Selection

If your program uses only a small fraction of the virtual address space, having a multi-level page table requires Reset Selection

Section 9.7.2 talks about how linux keeps track of memory regions with regard to read/write/execute permissions and shared memory. That information is also in the page table entries. Why should there be vm_area_structs if the same information is in the page table? Reset Selection

Section 9.9 reviews how malloc and free work. One implementation of malloc and free has free do nothing and malloc simply keep a single pointer it increments each time it is called. This implementation has Reset Selection

Section 9.10 discusses garbage collector. These often perform reachability analysis, tracing all pointers recursively to find what parts of allocated memory are actually usable. The reachability analysis starts assuming that what is reachable? Reset Selection

A cache maps an address to a value. Virtual memory maps an address to another address. Which kind of cache is virtual memory (i.e., page tables, not the TLB) organized the most like? Reset Selection

Let V be the size of the virtual address space and P be the size of the physical memory. Which of the following is true? Reset Selection

A page table entry contains some permission information and some type of pointer. If our program is trying to dereference a 32-bit integer value stored in memory, page tables accessed along the way could point to (select all that apply)

	A.	a page of data
	B.	another page table
	C.	some part of disk
	D.	the 32-but integer in question

Which type of exception does *not* use the exception table? Reset Selection

Which type of exception can occur without any particular instruction being the cause of the exception? Reset Selection

Which type of exception has an instruction that always causes it? Reset Selection

Which type of exception has an instruction that sometimes causes it and sometimes runs without causing it? Reset Selection