﻿ CS 3330: Computer Architecture

# CS 3330: Past Quizzes

This page does not represent the most current semester of this course; it is present merely as an archive.

## Fall 2014 Quiz 1:

Convert 0x93 to binary (your answer should consist of exactly 8 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 1.011 in decimal?

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits . What is the exponent? (your answer should consist of exactly 3 characters, each either 0 or 1)

Consider encoding 2.5 as a floating point number with 3 exponent bits (bias = 3) and 3 fraction bits. What is the fraction? (your answer should consist of exactly 3 characters, each either 0 or 1)

(Thought question; not part of your grade). Consider a C-style float x that is between 1e-20 and 1e20. Let the low-order bit be called bit 0 and the sign bit bit 31. There is one bit that is guaranteed to be different between x and 4*x; which bit is it? (your answer should be a number between 0 and 31)

## Fall 2014 Quiz 2:

Convert 0xdad to binary (your answer should consist of exactly 12 characters, each either 0 or 1)

Assume x is an 8-bit twos-compliment integer. What is the numeric value of x + ~x (in decimal)?

What is the binary number 11.101 in decimal?

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the exponent? (your answer should consist of exactly 4 characters, each either 0 or 1)

Consider encoding -5.5 as a floating point number with 4 exponent bits (bias = 7) and 5 fraction bits. What is the fraction? (your answer should consist of exactly 5 characters, each either 0 or 1)

(Thought question; not part of your grade). In two's-compliment there is one (and only one) number that is it's own additive inverse (i.e., x = -x). What is that number for 6-bit numbers? (your answer should be exactly 6 characters, each either 0 or 1)

## Fall 2014 Quiz 3:

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x1f - i for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10

The registers used in the questions have the following initial values:

eax = 0x03020100
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x03020100 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

 True False
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After executing "movl %ecx, (%esp)", which of the following changes?
 A. the contents of memory addresses 5 through 8 B. the contents of memory addresses 8 through 11 C. the contents of memory addresses 9 through 12 D. the contents of memory addresses 12 through 15 E. the contents of register ecx F. the contents of register esp
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After executing "popl %eax", what is the value in register eax?
 A. 0x14151617 B. 0x17161614 C. 0x1718191a D. 0x1a191817
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After executing "pushl %eax", what is the value in register esp?
 A. 4 B. 7 C. 8 D. 9 E. 12
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After executing "pushl %eax", what part of memory now contains 0x03020100?
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## Fall 2014 Quiz 4:

Each question presents one assembly operation and asks what it does. All questions assume the following initial configuration:

Memory at byte i contains 0x20 + ( * 3)%0xf for i between 0 and 15; that is

address:       0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
Memory (hex): 20 23 26 29 2c 2f 22 25 28 2b 2e 21 24 27 2a 2d

The registers used in the questions have the following initial values:

eax = 0x11223344
ecx = 0xc
esp = 8

Assume the configuration resets between each question, so that (for example) even if question 1 changes eax, eax has 0x11223344 in it again for question 2.

Both the choices presented for each multiple-choice question and the questions themselves are presented in sorted order based on the text of the question or choice. There is no other meaning to the ordering.

This quiz is open-book. You may use a calculator of computer if you wish. Do not consult with others, including others located on the Internet.

I made this a question so it will show up on the page. You don't need to answer it.

 True False
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After executing "movl (%esp), %ecx", which of the following changes?
 A. the contents of memory addresses 5 through 8 B. the contents of memory addresses 8 through 11 C. the contents of memory addresses 9 through 12 D. the contents of memory addresses 12 through 15 E. the contents of register ecx F. the contents of register esp
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After executing "popl %eax", what is the value in register eax?
 A. 0x212e2b28 B. 0x2825222f C. 0x282b2e21 D. 0x2f222528
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After executing "popl %eax", what is the value in register esp?
 A. 4 B. 7 C. 8 D. 9 E. 12
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After executing "pushl %eax", what is in memory at byte 8?
 A. 4 B. 8 C. 12 D. 0x11 E. 0x28 F. 0x44
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## Fall 2014 Quiz 5:

Section 4.2.2 defines the HCL for bit-equality to be

bool eq = (a && b) || (!a && !b);

Section 4.2.3 defines the HCL for word-equality to be

bool Eq = (A == B);

Assume we have two-bit words, so A is made of bits a1 and a0 and B is made of bits b1 and b0. Which of the following defines the bit-level implementation of word-level equality (A == B)?

 A. eq = (a0 == b0) && (a1 == b1); B. eq0 = (a0 && b0) || (!a0 && !b0);  eq1 = (a1 && b1) || (!a1 && !b1); C. eq = ((a0 && b0) || (!a0 && !b0)) && ((a1 && b1) || (!a1 && !b1)); D. eq0 = (a0 == b0); eq1 = (a1 == b1);
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On page 358 we see the following HCL:

int Out4 = [
!s1 && !s0 : A; # 00
!s1        : B; # 01
!s0        : C; # 10
1          : D; # 11
];

The text following this notes "the selection can sometimes be simplified, since only the first matching case is selected. For example, the second expression can be written !s1, rather than the more complicated !s1 && s0, since the only other possibility having s1 equal to 0 was given as the first selection expression." In other words, the above could have been written as

int Out4 = [
!s1 && !s0 : A; # 00
!s1 &&  s0 : B; # 01
s1 && !s0 : C; # 10
s1 &&  s0 : D; # 11
];

without changing its meaning in any way.

Which of the following pieces of C code allow this same kind of flexibility in how we write the boolean expressions?

(Note: more than one of the following options is "correct" and will receive full credit)

 A. if (!s1 && !s0) Out4 = A; else if (!s1)   Out4 = B; else if (!s0)   Out4 = C; else if (1)     Out4 = D; B. if (1)          Out4 = D; if (!s0)        Out4 = C; if (!s1)        Out4 = B; if (!s1 && !s0) Out4 = A; C. Out4 = !s1 && !s2 ? A      : !s1        ? B      : !s0        ? C      :              D; D. if (!s1 && !s0) Out4 = A; if (!s1)        Out4 = B; if (!s0)        Out4 = C; if (1)          Out4 = D;
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Section 4.2.2 defines the HCL for bit-MUX to be

bool out = (s && a) || (!s && b);

Section 4.2.3 defines the HCL for word-MUX to be

int Out = [
s : A;
1 : B;
];

Assume we have two-bit words, so A is made of bits a1 and a0 and B is made of bits b1 and b0. Which of the following defines the bit-level implementation of word-level MUX  ([s: A; 1:B;])?

 A. out0 = (s && a0) || (!s && b0); out1 = (s && a1) || (!s && b1); B. out = ((s && a0) || (!s && b0)) && ((s && a1) || (!s && b1)); C. out0 = (s0 && a0) || (!s0 && b0); out1 = (s1 && a1) || (!s1 && b1); D. out = ((s0 && a0) || (!s0 && b0)) && ((s1 && a1) || (!s1 && b1)); E. out = ((s && a0) || (!s && b0)) || ((s && a1) || (!s && b1)); F. out = ((s0 && a0) || (!s0 && b0)) || ((s1 && a1) || (!s1 && b1));
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## Fall 2014 Quiz 6:

Assume S is a non-pipelined system and P is a pipelined system. Pipelining increases both throughput and latency. Which of the following cases exemplify these principles? Check all that apply (if any do)
 A. It takes twice as long for P to answer a single sum as it takes S B. It takes twice as long for S to answer a single sum as it takes P C. S can do 150 sums in the same time it takes P to do 100 D. P can do 150 sums in the same time it takes S to do 100

What is meant by "nonuniform partitioning" and why is it a problem?
 A. It means the logic between the registers may vary in size; it is a problem because we have to run the clock slow enough for the biggest block. B. It means the size of the register file between each stage of the pipe varies in size; it is a problem because we have to run the clock slow enough for the biggest register file. C. It means the time needed to compute each operation varies; it is a problem because we have to run the clock slow enough for the slowest operation. D. It refers to the solution to the problem of harmonic oscillations that can occur if every stage of the pipeline is the same size: we make the stages nonuniform to prevent this buildup.
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Diminishing returns means that the more pipeline stages there are, the less benefit we get from adding more stages. Why is this?
 A. The more stages you have, the more non-uniform partitioning matters. B. The throughput doesn't have diminishing returns but once the pipe is deep enough the latency really matters a lot. C. Once the stages get too small we can't meaningfully chop it into smaller pieces anymore. D. As the stages become smaller the delay of the registers between each stage becomes more and more significant.
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## Fall 2014 Quiz 7:

Compare DRAM and SRAM. Check the true statements from the following:
 A. DRAM is cheaper than SRAM B. DRAM is faster than SRAM C. you have to refresh (read and re-write) DRAM to keep values in it D. you have to refresh (read and re-write) SRAM to keep values in it E. DRAM is more likely to be used for main memory than for on-chip caches F. SRAM is more likely to be used for main memory than for on-chip caches

Suppose a single address sent to the memory module retrieves 128 bits of data. That data is probably retrieved by
 A. a single 128-bit supercell in a memory chip B. combining all of the supercells in a single row of a memory chip C. combining one supercell from each of several memory chips D. none of the above: there's no such thing as a supercell
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It is typical for the I/O Bridge to be connected to three buses: the system bus, the memory bus, and the I/O bus. It routes a signal between pairs of these busses; the figures on pages 569, 570, and 578 show examples of

• System-to-memory (memory write), and

What is an example of memory-to-I/O?

 A. load an image into the graphics adapter B. process a key being pressed C. perform a disk write D. none of the above
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## Fall 2014 Quiz 8:

Compare DRAM and SRAM. Check the true statements from the following:
 A. DRAM uses more transistors per bit than SRAM B. DRAM uses a capacitor to store a value C. Typically a computer has more DRAM than SRAM

Reading a supercell takes two memory controller operations. In between the two the intermediate data is stored in
 A. a pipeline register B. the memory chip C. the memory controller
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A disk never sends memory to the CPU itself, instead sending it to memory. How does the CPU discover the data is there?

 A. it periodically has the I/O controller ask the memory if it got the data B. it periodically has the I/O controller ask the disk if it sent the data C. the memory has the I/O controller interrupt the CPU when the data arrives D. the disk has the I/O controller interrupt the CPU when the data is sent
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## Fall 2014 Quiz 9:

One reason that arrays can be faster than linked lists is that their elements are adjacent to one another in memory, where linked list elements may be scattered across widely varying addresses. This is an example of
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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Suppose you have a program that often needs several kilobytes of temporary memory. Re-using the same temporary memory each time can be faster than using different temporary memory each time because of
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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Consider two programs; one runs in a small loop, the other invokes several dozen functions each one. Assuming the amount of work is similar, the loop will almost certainly run faster. At least some of that speed difference is due to
 A. spatial locality B. temporal locality C. both spatial and temporal locality D. neither spatial nor temporal locality
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"Cache" is pronounced like
 A. cash B. catch C. caysh D. caytch E. cashee F. catchee G. cayshee H. caytchee I. cashay J. catchay K. cayshay L. caytchay
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If we find the data we want in a cache, we call that a
 A. cache find B. cache hit C. cache success
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If we fail to find data in a cache because we have never accessed the data before, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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If we fail to find data in a cache even though we access only a few bytes since we last accessed that same data, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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If we fail to find data in a cache because we've read too much data since we last accessed that same data, we call that a
 A. capacity miss B. cold miss C. conflict miss D. forced miss E. smart miss F. stupid miss G. warm miss
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## Fall 2014 Quiz 10:

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. If addresses are 32 bits long, how large is the tag stored with each line? Enter your answer as a non-negative integer without leading zeros. ____

Consider a cache with 1-byte words, 4-word blocks, 2-line sets, and 64 sets in total. Ignoring metadata like valid bits and tags, how many bytes of data does the cache store? Enter your answer as a non-negative integer without leading zeros. ____

Suppose a cache can store 64KB of data and is organized with 2-line sets. What is the largest amount of data that cache can serve without encountering a conflict miss?
 A. None B. 32KB C. 64KB D. 128KB E. Unlimited
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Assume that cache F is fully associative and cache D is direct-mapped. Assume the two caches have the same address space and the same total data capacity.
 A. F has fewer tag bits than D B. F has more tag bits than D C. F has the same number of tag bits as D D. You'd need more information to be able to tell which has more tag bits.
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Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 16 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data scattered in a deterministic but random-looking pattern across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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Process A accesses 32 bytes of data in order evenly spaced across addresses 0x00 through 0xff. Assume that cache F is fully associative (using a least-recently-used policy) with 32 lines of 4 bytes each, and cache D is direct-mapped with 32 lines of 4 bytes each. Assume we A twice and measure the cache misses the second time.
 A. F will probably have fewer cache misses than D B. D will probably have fewer cache misses than F C. They will have about the same number of cache misses
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## Fall 2014 Quiz 11:

Loop unrolling is usually used to remove what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Inline substitution (also called "inlining") is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Using multiple accumulators is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Loop blocking is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Adding local variables is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Reassociation of operators is usually used to reduce what source of inefficiency?
 A. condition checking overhead B. data dependencies C. poor branch prediction D. poor cache locality E. procedure call overhead F. unnecessary memory references
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Which of the following techniques depend on a pipelined processor's ability to work on several instructions at once, and thus would not work in a non-pipelined processor? Check all that apply.
 A. loop unrolling B. inlining C. multiple accumulators D. loop blocking E. local variables F. reassociation

Section 5.2 of the textbook discusses CPE (cycles per element, also called cycles per execution or cycles per instruction in other sources). Their discussion suggests that if I have code with 20 CPE and run it on a problem where my algorithm executes on 100 elements, I should expect the runtime to be:
 A. 0-50 cycles B. 50-220 cycles C. 220-1100 cycles D. 1100-2200 cycles E. more than 2200 cycles
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## Fall 2014 Quiz 12:

When discussing virtual memory, a single page (check all that apply)
 A. can be in-memory, on-disk, or unallocated B. can be partly in-memory and partly not in-memory C. contains a contiguous block of virtual addresses D. is a fixed-size block of bytes E. is mapped to a contiguous block of physical addresses

From the perspective of a running application, virtual memory looks like
 A. a collection of scattered address pages B. a single flat address space C. nothing; virtual memory is not something application code interacts with
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From the perspective of the operating system, virtual memory looks like
 A. a collection of scattered address pages B. a single flat address space C. nothing; virtual memory is not something the operating system interacts with
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As used by our textbook, a "cached" virtual page is one that is
 A. not (yet) in memory B. partly but not fully in memory C. fully in memory D. fully in memory and at least partly some memory cache E. fully in memory and fully in some memory cache
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What is the difference between "caching" a page, "swapping in" a page, and "paging in" a page? Check all that apply.
 A. caching refers to the cache; the other two refer to memory instead. B. swapping means some memory comes in and some other memory goes out; the other two can refer to something coming in without anything going out. C. paging means moving an entire page of memory; the other two can refer to just parts of a page instead. D. there is no difference; they mean the same thing

## Fall 2014 Quiz 13:

A page table is
 A. an array B. a binary tree C. a hashmap D. a linked list E. a more complicated data structure F. a set-associative cache G. none of the above H. it varies depending on the specific chip and OS.
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A translation lookaside buffer (TLB) is
 A. an array B. a binary tree C. a hashmap D. a linked list E. a more complicated data structure F. a set-associative cache G. none of the above H. it varies depending on the specific chip and OS.
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For a multi-level page table, the first level page table(s) of process P
 A. must be stored in physical memory whether P is running or not B. must be stored in physical memory if P is currently running C. may be stored in physical memory or paged out to disk whether P is running or not
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For a multi-level page table, the second level page table(s) of process P
 A. must be stored in physical memory whether P is running or not B. must be stored in physical memory if P is currently running C. may be stored in physical memory or paged out to disk whether P is running or not
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Core i7 memory uses four virtual page numbers because it's MMU has a four-level page table hierarchy. Consider translating a single virtual address into a physical address. Which following numbers of page table accesses could occur during that translation? If different states of the caches and so on could result in different numbers of page table lookups, check multiple answers.
 A. 0 B. 1 C. 2 or 3 D. 4 E. 5 or more

## Fall 2014 Quiz 14:

When the CPU is interrupted, how does it know which device created the interruption?
 A. All interrupts are handled the same way, so it doesn't matter which device interrupted it B. Each device uses a different interrupt pin C. It's the most recent one the CPU asked to interrupt it D. It's the operating system's job to ask the devices what they need and figure out which one interrupted the CPU, not the CPU's E. The interrupting device puts its identity on the system bus before interrupting
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What distinguishes a fault from a trap? Check all that apply
 A. A trapping instruction does not get re-run after the trap is handled, but a faulting instruction does get re-run after the fault is handled B. A trapping instruction always creates an exception, but a faulting exception only sometimes creates an exception C. Traps are used primarily to talk to the operating system, faults are used primarily to recover from errors D. Traps are handled by the OS, faults are not E. Traps are not handled by the OS, faults are

The assembly instruction "int x" used to make system calls only accepts a 1-byte (256-value) argument x, but Linux uses it to support over 300 system calls. How does it do that?
 A. Linux tells them apart by branching based on the condition code registers B. Linux tells them apart by looking at what the PC was when the system call was made C. Linux tells them apart by reading a value off of the system bus D. Linux tells them apart by reading a value off of the interrupt pins E. Linux tells them apart by the contents of %eax F. There aren't really 300+ system calls; many of them are aliases for one another
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## Fall 2014 Quiz 15:

In hardware, everything runs in parallel unless data dependencies prevent that
 A. True B. False
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In software, everything runs in parallel unless data dependencies prevent that
 A. True B. False
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The hardware is aware of the program stack
 A. True B. False
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Put the following (listed in alphabetical order) in order of importance when optimizing code that operates on very large arrays: B = Body of loop optimization (function inlining, efficient math), C = Cache locality, O = big-O of algorithm used. Answer as three capital letters, no spaces, such as BCO

How does knowing you have a pipelined processor change the code you write?
 A. it suggests optimizations like adding local variables B. it suggests optimizations like loop unrolling C. it suggests optimizations like loop reordering D. it suggests optimizations like multiple accumulators
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The operating system is involved when there is a cache miss
 A. True B. False
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The operating system is involved when there is a page fault
 A. True B. False
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## Spring 2015 Quiz 1:

: Which two of the following four binary number formats are used by modern computer hardware?
 A. one's-complement integer B. sign-magnitude integer C. two's-complement integer D. unsigned integer

: Binary 0011 + binary 1001 = ____ (answer in binary with exactly four characters, each either 0 or 1)

: 0x3f ^ 0x15 = ____ (answer in lower-case hexidecimal with exactly two characters, each between 0 and f)

: Which of the following is true for all possible values of unsigned x?
 A. !!x == x B. !!x == ((x<<31)>>31) C. (x+x) > x D. (x^(x+1)) == 1 E. x + 1 > x F. more than one of the above is true for all x G. none of the above are true for all x
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## Spring 2015 Quiz 2:

If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, which of the following numbers (shown in binary) is the largest finite number it can represent?
 A. 1.11 B. 1.111 C. 11.1 D. 11.11 E. 111 F. 111.1
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If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, what is the smallest positive number (> 0) it can represent? Answers are shown in binary
 A. 0.001 B. 0.0001 C. 0.00001 D. 0.000001 E. none of the above
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Consider the following eight binary C operators: + - * / % ^ & |. Consider the 32 bits representing the result of "x operator y", where x and y are each either int or unsigned int. For how many of these 8 operators will those bits differ depending on the singed/unsigned nature of x and y? Your answer should be a single digit between 0 and 8:

## Spring 2015 Quiz 3:

How many total bytes of data can be stored in the (integer) IA32 program registers at one time? (a program register is one you can use as an operand when in programming in IA32 assembly)
 A. 4 B. 8 C. 16 D. 32 E. 48 F. 56
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The textbook uses ATT-format assembly, the default for most GNU tools. Some other tools use Intel-format assembly instead. Each of the following is true for only one of the two formats. Check those that are true of ATT-format assembly:
 A. there is a separate opcode for adding 32-bit values (addl) and 16-bit values (addw) B. register names are preceded by a percent-sign (e.g. %eax) C. memory addresses are written with square brackets and math operators (e.g. [edx+4]) D. add A B (where A and B are registers) stores the sum of A and B into register A E. sub A B (where A and B are registers) evaluates B - A, not A - B

"pushl %eax;" is the same as
 A. addl \$4 %esp; movl %eax (%esp); B. addl \$-4 %esp; movl %eax (%esp); C. movl %eax (%esp); addl \$4 %esp; D. movl %eax (%esp); addl \$-4 %esp;
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The "imul" instruction has only one operand, as in "imul \$101;", but the multiplication operation is implements requires two operands. The second operand is
 A. %eax B. %esp C. (%esp) D. 12(%ebp) E. the same as the first (i.e., imul squares its operand) F. none of the above
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## Spring 2015 Quiz 4:

In Java, C++, etc, there are types: a String is not the same as a Scanner, and so on. Types are distinct from "meaning": int x might *mean* your age and int y might *mean* your number of siblings, but the language doesn't stop you from saying "x = y" because they are both *type* int. In assembly
 A. There are no types at all B. Integers and floating-point numbers are distinct, but otherwise no types C. There are only a few built-in types, but assembly lets you create new ones D. There types like other languages have E. There are more types than most other languages
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IA32 (also called x86) is CISC, not RISC, because (check all that apply)
 A. each instruction takes the same time to execute B. it has a lot of instructions or opcodes C. math operations can only operate with register operands (not memory) D. some instructions are encoded in just a single byte while others are much longer E. some instructions provide high-level abstractions, hiding lots of action under the hood F. there are many program registers

## Spring 2015 Quiz 5:

Two of the following are equivalent to the single-bit mux that the book denotes [ s : A; 1 : B; ], the other two are not equivalent to that mux. Mark the two that are:
 A. (s == A) || (s ^ B) B. (s == (A && B)) || (s != (A || B)) C. s ? A : B D. (s && A) || (!s && B)

Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware retrieve the value stored in register %edx?
 A. Fetch B. Decode C. Execute D. Memory E. Writeback
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Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware decide where the result will be stored?
 A. Fetch B. Decode C. Execute D. Memory E. Writeback
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Not all stages are invovled in executing all instructions. Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. Which (if any) stages are not involved in handling this instruction? Check any that apply
 A. Fetch B. Decode C. Execute D. Memory E. Writeback

## Spring 2015 Quiz 6:

Which of the following operations read a value from memory? Check all that apply
 A. nop B. rrmovl C. irmovl D. rmmovl E. mrmovl F. OPl G. jXX H. call I. ret J. pushl K. popl

Which of the following operations write a value to memory? Check all that apply
 A. nop B. rrmovl C. irmovl D. rmmovl E. mrmovl F. OPl G. jXX H. call I. ret J. pushl K. popl

Which of the following operations write a value to a program register? Check all that apply
 A. nop B. rrmovl C. irmovl D. rmmovl E. mrmovl F. OPl G. jXX H. call I. ret J. pushl K. popl

Which of the following operations read a value from a program register? Check all that apply
 A. nop B. rrmovl C. irmovl D. rmmovl E. mrmovl F. OPl G. jXX H. call I. ret J. pushl K. popl

The book discusses using the ALU just to forward values for some operations (e.g., their irmovl has the ALU compute 0 + valC) and to do math for other operations. The forwarding is just a design choice and could have been done otherwise, but the math is intrinsic to the operation of Y86. Which of the following operations use the ALU to do math?
 A. nop B. rrmovl C. irmovl D. rmmovl E. mrmovl F. OPl G. jXX H. call I. ret J. pushl K. popl

When building a chip, we can pick any clock speed we want; the goal is to make it as fast as we can while still being slow enough that no register grabs onto a value before that value has stabilized. Which of the following instructions would be most likely to determine the SEQ clock speed?
 A. nop B. rrmovl C. OPl D. jXX E. popl
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## Spring 2015 Quiz 7:

In general, pipelining
 A. decreases latency and decreases throughput B. decreases latency and increases throughput C. increases latency and decreases throughput D. increases latency and increases throughput
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Nonuniform partitioning happens when
 A. in some stages, the clock cycle is longer than the stage requires B. some stages have more work to do than others C. work cannot be evenly divided between registers D. all of the above E. none of the above
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Suppose instruction A is followed by instruction B in the assembled code. There is a hazard between A and B if (check all that apply)
 A. A's inputs depend on B's outputs B. B's inputs depend on A's outputs C. Whether A runs depends on the outcome of B D. Whether B runs depends on the outcome of A

In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "stall" signal?
 A. 0 B. 1 C. 2 D. 3 E. 4 F. 5
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In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "bubble" signal?
 A. 0 B. 1 C. 2 D. 3 E. 4 F. 5
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## Spring 2015 Quiz 8:

Which of the following is orders from slowest to fastest?
 A. Magnetic disk, Solid-state disk, DRAM, SRAM B. Magnetic disk, Solid-state disk, SRAM, DRAM C. Solid-state disk, Magnetic disk, DRAM, SRAM D. Solid-state disk, Magnetic disk, SRAM, DRAM E. None of the above is the correct ordering
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Data can be stored in program registers, memory, or disk. Which of the following technologies (if any) is/are most commonly associated with memory? Check all that apply
 A. D Flip-flops B. DRAM C. Ethernet D. Magnetic disk E. Solid-state disk F. SRAM

Which of the following needs to be read and then re-written periodically in order to retain its storage? Check all that apply
 A. DRAM B. Magnetic disk C. Solid-state disk D. SRAM

Which of the following needs power in order to retain its storage? Check all that apply
 A. DRAM B. Magnetic disk C. Solid-state disk D. SRAM

## Spring 2015 Quiz 9:

Code has good spatial locality if
 A. each memory read is far from the address of the previous read B. each memory read is near the address of the previous read C. it uses a lot of memory overall D. it uses little memory overall E. there are gaps of unused memory padding the parts of memory it uses F. there are no gaps of unused memory between parts of memory it does use
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Code has good temporal locality if
 A. it accesses each memory location only once B. some memory is accessed repeatedly, and all accesses happen one after the other C. some memory is accessed repeatedly, and each access happens some time after the others
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Which of the following describes the kind of caching that the memory hierarchy implements?
 A. after computing a value once, you store the result in memory to prevent having to compute it again later B. once there is a market for your assets you sell them C. you keep many copies of your data in different locations so that if one system fails you don't loose it all D. you store most of your data in big, cheap memory but the most important stuff gets backed up onto a smaller, more expensive, but more durable memory E. all of the above describe memory hierarchy caching F. none of the above describe memory hierarchy caching
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Section 6.4 talks about blocks, caches, lines, and sets. Which one is contained by which other? Answer with four capital letters (B, C, L, and S) concatenated from outermost-to-innermost; for example, if believe that blocks contain caches which contain lines which contain sets, your answer should be BCLS

In a set-associative cache, which of the following can be determined from the memory address and cache organization alone (i.e., without knowing the cache contents)? Check all that apply.
 A. block offset B. set index C. tag D. which byte in the cache to access E. which line in the cache to access F. which set in the cache to access G. valid bit

Quiz 10 was not given

## Spring 2015 Quiz 11:

Which of the following is expected to run fastest? Assume N and M are large numbers.
 A. for(i=0; i
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Which of the following is expected to run fastest? Assume N is a large number.
 A. for(i=0; i
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Which of the following are *not* tips for optimizing memory accesses given in the textbook? Check all that apply
 A. focus on the common case B. focus on inner loops C. get in the habit of performing cache optimizations everywhere D. reduce cache misses even if it means a few more memory accesses E. try to read memory in sequential order F. try to use data as often as possible once it has been read into memory

## Spring 2015 Quiz 12:

We want to loop over all i, j, and k (between 0 and 10240) and run the following: a[i][j] = b[i][k] * c[k][j] In order to maximize cache locality, in what order should the loops be placed?
 A. for(i) for(j) for(k) B. for(i) for(k) for(j) C. for(j) for(i) for(k) D. for(j) for(k) for(i) E. for(k) for(i) for(j) F. for(k) for(j) for(i) G. it doesn't matter
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Which of the following is describes the situations in which you should optimize your code for cache locality?
 A. always B. never C. any time it doesn't make code less readable D. none of the above is correct
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Using a #define IDX (like those shown in class) and a 1D array instead of a 2D array is done because
 A. it is easier to create a 1D array B. it is easier to read code with IDX C. it wastes less space D. it ensures locality of neighboring rows
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## Spring 2015 Quiz 13:

Suppose function A is O(n) and for n=1 takes 100ms; function B is O(n^2) and for n=1 takes 1ms. Which of the following n do you expect to be the smallest for which A is faster than B?
 A. 2 B. 20 C. 200 D. 2000 E. A is always faster than B F. A is never faster than B G. insufficient information to tell
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Register spilling is when
 A. quantum effects cause register values to pollute one another B. the value in a register gets so large it spills over into another register too C. the value in a register gets to large it spills over the end of the register, causing some bits to be lost D. there are so many local variables that some of them cannot be stores in registers E. you run out of space in memory so you store some values in registers instead
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Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
 A. x1 * x2 * (x3 * x4) B. x1 * (x2 * x3) * x4 C. (x1 * x2) * x3 * x4 D. They're all the same
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Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
 A. for(i=0; i<99; i+=1) a[i] = i; B. for(i=0; i+1<99; i+=1) { a[i] = i; i+=1; a[i] = i; } a[98] = 8; C. for(i=0; i+3<99; i+=1) { a[i] = i; i+=1; a[i] = i; i+=1; a[i] = i; i+=1; a[i] = i; } for(; i<99; i+=1) a[i] = i; D. They're all the same
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## Spring 2015 Quiz 14:

If a virtual page is allocated and in physical memory, how do we discover the physical page number?
 A. It's the same as the virtual page number B. The MMU finds it in a page table C. The operating system assigns it after loading the page from disk D. The operating system finds it in a page table E. We don't; there is no physical page number in this situation
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If a virtual page is allocated but is not in physical memory, how do we discover the physical page number?
 A. It's the same as the virtual page number B. The MMU finds it in a page table C. The operating system assigns it after loading the page from disk D. The operating system finds it in a page table E. We don't; there is no physical page number in this situation
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If a virtual page is not allocated, how do we discover the physical page number?
 A. It's the same as the virtual page number B. The MMU finds it in a page table C. The operating system assigns it after loading the page from disk D. The operating system finds it in a page table E. We don't; there is no physical page number in this situation
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## Spring 2015 Quiz 15:

Page tables are stored in
 A. a special bank of registers B. a special memory chip set aside for page tables C. each process's virtual address space D. main memory's physical address space E. the page table base register (PTBR)
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If you have a single-level page table, the amount of space it requires varies based on how many pages are in use.
 A. True B. False
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If you have a multi-level page table, the amount of space it requires varies based on how many pages are in use.
 A. True B. False
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If your program uses 100% of the virtual address space (even the parts normally not used), having a multi-level page table requires
 A. less space than a single-level page table B. more space than a single-level page table C. the same amount of space as a single-level page table
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If your program uses only a small fraction of the virtual address space, having a multi-level page table requires
 A. less space than a single-level page table B. more space than a single-level page table C. the same amount of space as a single-level page table
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## Spring 2015 Quiz 16:

Section 9.7.2 talks about how linux keeps track of memory regions with regard to read/write/execute permissions and shared memory. That information is also in the page table entries. Why should there be vm_area_structs if the same information is in the page table?
 A. having two copies provides fault tolerance if one fails B. one is for read/write/execute permissions, the other for user/kernel permissions C. one is for the MMU, the other for the OS D. the vm_area_struct is how you access a page table entry in C
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Section 9.9 reviews how malloc and free work. One implementation of malloc and free has free do nothing and malloc simply keep a single pointer it increments each time it is called. This implementation has
 A. high throughput and high utilization B. high throughput and low utilization C. low throughput and high utilization D. low throughput and low utilization
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Section 9.10 discusses garbage collector. These often perform reachability analysis, tracing all pointers recursively to find what parts of allocated memory are actually usable. The reachability analysis starts assuming that what is reachable?
 A. the most recent n allocation for some constant n B. the pointers in every stack frame ever allocated C. the pointers in every stack frame pushed but not yet popped D. the pointers in the current stack frame E. the pointers in the heap F. the pointers in the heap that have been allocated but not yet deallocated G. the pointers in the heap that have ever been allocated
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## Spring 2015 Quiz 17:

A cache maps an address to a value. Virtual memory maps an address to another address. Which kind of cache is virtual memory (i.e., page tables, not the TLB) organized the most like?
 A. direct-mapped B. set-associative C. fully-associative
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Let V be the size of the virtual address space and P be the size of the physical memory. Which of the following is true?
 A. V < P B. V <= P C. V == P D. V >= P E. V > P F. any of the above could be true
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A page table entry contains some permission information and some type of pointer. If our program is trying to dereference a 32-bit integer value stored in memory, page tables accessed along the way could point to (select all that apply)
 A. a page of data B. another page table C. some part of disk D. the 32-but integer in question

## Spring 2015 Quiz 18:

Which type of exception does *not* use the exception table?
 A. fault B. interrupt C. trap D. all of the above use the exception table E. none of the above use the exception table
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Which type of exception can occur without any particular instruction being the cause of the exception?
 A. fault B. interrupt C. trap D. all of the above can occur without any particular instruction being the cause of the exception E. none of the above can occur without any particular instruction being the cause of the exception
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Which type of exception has an instruction that always causes it?
 A. fault B. interrupt C. trap D. all of the above have an instruction that always causes it E. none of the above have an instruction that always causes it
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Which type of exception has an instruction that sometimes causes it and sometimes runs without causing it?
 A. fault B. interrupt C. trap D. all of the above have an instruction that sometimes causes it and sometimes runs without causing it E. none of the above have an instruction that sometimes causes it and sometimes runs without causing it
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