Memory Bandwidth Optimizations for Wide-Bus Machines

Michael A. Alexander
Mark W. Bailey
Bruce R. Childers
Jack W. Davidson
Sanjay Jinturkar

Abstract: One of the critical problems facing designers of high performance processors is the disparity between processor speed and memory speed. This has occurred because innovation and technological improvements in processor design have outpaced advances in memory design. While not a panacea, some gains in memory performance can be had by simply increasing the width of the bus from the processor to memory. Indeed, high performance microprocessors with wide buses (i.e., capable of transferring 64 bits or more between the CPU and memory) are beginning to become commercially available (e.g. MIPS R4000, DEC Alpha, and Motorola 88110). This paper discusses some compiler optimizations that take advantage of the increased bandwidth available from a wide bus. We have found that very simple strategies can reduce the number of memory requests by 10 to 15 percent. For some data and compute intensive algorithms, more aggressive optimizations can yield significantly higher reductions. The paper describes the code generation strategies and code improvement techniques used to take advantage of a prototypical wide bus microprocessor.

Maintained by Mark Bailey (bailey@virginia.edu)

Last modified: Sat Jan 11 11:44:42 1997