Implementing a Gated Clock Methodology in Phased Logic
Most of the electronic systems used today for control, computation, and communication are digital systems. As digital systems become larger and their clock speeds grow, designing systems has become increasingly complex . Designers must take into account more low-level timing details in the high-level view of a system, because they must assure that every part of their circuit can complete its task in the time allotted to it by the global clock signal. These added details greatly increase the difficulty of their task. One solution to this problem is to avoid the use of a global clock altogether. This is the fundamental idea behind asynchronous circuit design.
The asynchronous design methodology that we are concerned with is Phased Logic (PL), introduced in . PL uses two wires for every signal; one for data and the other for timing. Every signal has a phase, which is determined by the parity of its two values. Each logic gate also has a phase. The output of each gate does not change until the phase of all of its input signals matches its own internal phase. When this occurs the gate updates its output signals and toggles its state, a process referred to as firing. In order to be sure that a circuit will behave properly, we must assure two things. First, the circuit must be live, meaning there is no way for the circuit to get stuck and cease operation. Second, the circuit must be safe, meaning there is no way for data to get lost by an input signal being updated before it has been processed. Adhering to these two criteria is relatively simple using the PL synthesis algorithm described in , and doing so will ensure that the circuit will behave as desired regardless of the delays in the gates and the wires.
Historically, performance and area have been the two most important factors in the design of digital circuits . However, as clocks become faster and portable electronics gain popularity, power consumption is becoming equally as important . One way to save power in synchronous circuit design is to use clock gating, which shuts off power to idle areas of a system by deactivating the clock signal to those areas. The analog to clock gating in PL is somewhat more complicated, because shutting off one area of a circuit can bring the entire circuit to a halt. This idea of clock gating in PL is referred to as conditional token flow in . Conditional token flow uses interface gates referred to as p2c (parent-to-child) and c2p (child-to-parent) to allow the flow of tokens (data) to continue in a parent PL system while a child system is deactivated. This has the potential to save power as well as increase performance if the deactivated subsystem is in the critical path of the system.
The designs of the p2c and c2p gates were introduced in . Each gate has both enable and data inputs, as well as a data output. A p2c gate will pass its data input on to the child when the enable signal is high but not when it is low. A c2p gate will pass its data input on to its data output when the enable signal is high, but will only change the phase of its data output when the enable signal is low. The design of the p2c gate was discussed in detail by Aydin in . Aydin's design broke up the p2c gate into six components: the C-Element, Enable Logic, Fire Generator, Feedback Generator, Child Phase module, and Output module. Using Petrify, Aydin generated the output equations for all of the components and was able to successfully simulate the functioning of the p2c gate. His design for this gate, and the similar c2p gate, will be used in our research.
Prof. Traver's earlier work with PL used a fine-grain mapping scheme in which every gate in a synchronous circuit was converted directly into a PL gate. The work discussed in , however, uses a coarse-grain mapping scheme in which blocks of logic from the synchronous circuit are wrapped with PL logic without modification to their internal structure. This scheme greatly simplifies the design process as circuitry from a preexisting synchronous system can be reused in its original form. This scheme also has a lower area overhead because less control logic needs to be introduced. For these reasons, the coarse-grain method will be used in this research.
Our proposed work is to investigate whether the conditional token flow method in Phased Logic offers the same power savings as clocked gating in synchronous design. To create a test environment, it will be necessary to develop a synchronous system that uses clock gating and then develop an equivalent PL system that uses conditional token flow. The first task therefore will be to choose a clock gating methodology, such as the activity-driven clock trees proposed in , and use it to implement a synchronous system, such as the ALU used in . Several clock gating methodologies exist, and it will be important to choose a methodology that is compatible with the course-grained PL approach. We will then convert the chosen system into a PL circuit using conditional token flow and the p2c and c2p gates described earlier. Running the same benchmarks on both of these systems will allow us to draw conclusions about the energy savings for a PL system using conditional token flow and a synchronous system using clock gating.
After completing this research, I will have a much better understanding of asynchronous circuit design and Phased Logic. As synchronous systems and their associated timing problems become increasingly complex, asynchronous circuits will likely become more and more practical. My knowledge in this area will therefore be very helpful in understanding and designing what could potentially be a very powerful concept in digital systems. This research will also help me become familiar with and understand the importance of energy efficient design. As portable electronics grow smaller and more popular, the importance of energy efficiency can only increase. Design of future electronics will require an in-depth knowledge of power saving techniques.