Using POSET Timing and ATACS for Synthesis and Verification of Phased Logic Wrappers
Cherrice Traver


A self-timed design methodology called Phased Logic (PL) has been developed over the last 5 years to address the difficulties of using a global clock for circuit level timing, while keeping a synchronous design framework. This methodology has been used to synthesize several designs, including a processor core, from their register transfer level descriptions to a netlist of standard cells. These designs have been compared favorably to their clocked equivalents. So far ad-hoc design techniques have been used to develop the asynchronous control structure (wrappers) in this methodology. As such, they have not been optimized or analyzed. Since these circuits are critical to the performance of PL systems, the objective of this work is to develop a formal specification of these circuits for the purpose of analysis and optimization.

PL circuits are automatically generated from a clocked netlist of combinational gates and storage elements. The resulting control structure preserves the synchronous nature of the original clocked system in that there is a one-to-one correspondence between clock cycles in the original netlist and computation cycles in the new control structure. Automated translation offers the substantial benefit that any current design methodology (tools, languages, etc) can be used to produce the clocked netlist. The mapping process partitions the clocked netlist into blocks with each block containing a mixture of combinational logic and register elements which form the computation function for the block. The computation element for a block can also be standard compute functions such as monolithic memories, multipliers, etc. Encapsulating the computation element is a wrapper consisting of a set of output latches and additional gating that executes the needed sequencing for the PL control scheme. It is this wrapper logic that is the focus of this work.

POSET timing is a timing analysis algorithm that can be applied to a wide class of asynchronous circuits. It forms the basis for synthesis of a timed Petri-net specification to a hazard-free gate level circuit. The specification is entered in a high level language, translated from the timed Petri-net to an orbital net representation, and then the POSET timing algorithm is used to find the state graph. A hazard-free implementation is constructed from the state graph using standard logic gates and C-elements.

The goal of this work is to use the ATACS design system, which includes the POSET timing algorithm, for both verification and synthesis of PL wrapper circuits. This will have advantages for both the Timed Circuit Research Group at the University of Utah and the PL researchers. The researchers at the University of Utah will gain additional results of the application of their tools, and the PL methodology will be improved through the development of optimized control circuits.



References:

  • R. Reese, M. Thornton and C. Traver, "A Coarse-grained Phased Logic CPU", Ninth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), Vancouver, BC, Canada, May 2003, pp 2-13.

  • Daniel H. Linder and James C. Harden, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," IEEE Transactions on Computers, vol. 45, pp. 1031-1044, Sept. 1996.

  • Other Phased Logic references can be found at http://www.erc.msstate.edu/mpl/projects/phased_logic/publications/

  • Chris J. Myers, Tomas G. Rokicki, Teresa H.-Y. Meng, POSET Timing and its Application to the Synthesis and Verification of Gate-Level Timed Circuits, IEEE Transactions on CAD, VOL. 18, NO. 6, JUNE 1999.

  • Other publications from the Myers Research Group can be found at http://www.async.ece.utah.edu/publications/