Orna Etzion and Yigal Zemach, Intel Corporation, IDC,
IA-32 Execution Layer is a technology that executes IA-32 applications on Intel® Itanium® processor family systems, through dynamic binary translation. IA-32 Execution Layer is running on top the host operating system and we describe how the same translator binary is used for both Windows* and Linux* systems. IA-32 Execution Layer uses 3 emulation phases technology which buys it about 60% of native performance on CPU2K Integer code. The translator is fully compatible and we describe how we cope with difficult corner cases without losing performance in the main stream. Solutions to several challenges, such as precise exception, self-modifying code, multi-threaded environment support, and debug support are discussed. We also describe how we enable a mixed mode running for Java applications that run on top of a native JVM but down-calls IA-32 code and conclude with solutions to some “real life” problems.
1.1. What is IA-32 Execution Layer
1.2. General Architecture
1.4. Handling of specific corner cases (SMC, DAZ, NX, …)- I suggest to remove from intro
1.5. IA-32 execution Layer performance
2. Multiple OS interaction
2.1. Single binary translation core for all Operating Systems
2.2. OS Glue layers
2.3. Launch and start-up
2.4. System calls
2.5. Synchronous and asynchronous events
3. Mixed Mode Execution for Java applications
3.1. Running under 64-bit JVM
3.2. Down-calls and up-calls
4. Precise Exception
4.1. Exceptions raised by the emulation
4.2. OS interaction for exception, signal, suspension
4.3. State recovery at different phases
4.4. Exceptions that needs to be ignored, postponed, or modified
4.5. Using state recovery for internal suspensions
4.6. DAZ support via exceptions handling
5. Multi-threading support
5.1. Thread creation and initialization
5.2. Thread termination
5.3. Thread suspension and synchronization
5.4. Translation invalidation under MT conditions: Garbage Collection, Page Permissions change.
5.5. “Application” threads and “native” threads
6. Debug architecture
6.1. Code breakpoints (INT3)
6.2. Set and Get context
6.3. Exception / Signal handling
6.4. Data breakpoints
7. Challenges beyond benchmarks
7.1. Module reuse
7.2. Memory ordering vs. scalability
7.3. SMC and writable code
7.4. NX support
Any audience with general understanding of dynamic / managed code environments. General SW concept understanding is assumed. Basic knowledge in compiler technology may be helpful.
Etzion Orna is a SW leader in Intel Corporation, IDC center, for the last 15 years. Orna worked on the development of compilers for IA-32 architecture, on binary instrumentation technology and in the last several years on the binary translation system for IA-32 applications on Itanium processor (IA-32 Execution Layer).
Zemach Yigal is a SW leader in Intel Corporation, IDC center, for the last 14 years. The products development he was involved in included SW tools for Intel’s various architectures (assemblers, linkers, decoders, GUI-assembler-assistance) and in the last few years one of the leaders of the binary translation technology.