The Fifteenth
International Conference on
Parallel
Architectures and Compilation Techniques
General Chair
Welcome Program
Chairs Welcome
Saturday, September 16
Sam Midkiff, Purdue
Maria
Garzaran, Illinois
Michael Perrone, IBM
Research
Applications, systems, and architecture (Website)
Cosimo Antonio Prete and Pierfrancesco
Foglia,
Sandro Bartonlini and Roberto Giorgi,
Tutorial 2: A Case
Study of a Physically Based Visual Simulation
Targeting Emerging Architectures and
Programming Models
Yahya Mirza, Aurora Borealis Software LLC
Sunday, September 17
Walid Najjar, UC-Riverside
Kathryn O'Brien, IBM Research
Tutorial 3: X10: Concurrent Object-Oriented Programming for Modern Architectures
Vijay Saraswat and Christoph von Praun, IBM
Research
Tutorial 5: IA-32
Execution Layer: Dynamic Binary
Translator from
IA32 to Intel Itanium Architecture
Orna Etzion and Yigal Zemach, Intel
in High Performance and Parallel
Applications
Ronald Mraz, Owl Computing Technologies,
Fabrizio
Petrini,
Matt Sottile,
Tutorial 4: Transactional
Programming in a Multi-Core Environment
Targeting Emerging Architectures and
Programming Models
Bratin Saha and Ali-Reza Adl-Tabatabai, Intel
Christos Kozyrakis, Stanford
Monday, September 18
8:15-8:30 Opening Remarks
Experiences with MapReduce, an Abstraction for
Large-Scale Computation: Slides,
Abstract
Architectural Support for Operating System-Driven
CMP Cache Management
·Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
Communist, Utilitarian, and Capitalist Cache Policies
on CMPs:
·Lisa R. Hsu, Steven K. Reinhardt, Ravishankar Iyer,
and Srihari Makineni
Core architecture Optimization for Heterogeneous Chip
Multiprocessors
·Rakesh Kumar, Dean M. Tullsen, and Norman P. Jouppi
Track 2 (Session 2): Program
Analysis and Optimization
Compiling for Stream Processing
·Abhishek Das, William J. Dally, and Peter Mattson
·Silvius Rus, Guobin He, Christophe Alias, and
A Two-Phase Escape Analysis for Parallel Java Programs
·Kyungwoo Lee and Samuel P. Midkiff
At the Boeing plant, there will be tours of the assembly lines where 747, 767, and 777 jets are manufactured. Part of the tour will be conducted in the world's largest building by volume: 472 million cubic feet / 13 million cubic metres. On the Boeing flight line, visitors will see airplanes in various stages of flight test and manufacture for airline customers around the world.
Tuesday, September 19 Morning
Challenges and Opportunities in the Post Single-Thread-Processor Era:
Slides, Abstract
Self-Checking
Instructions -- Reducing Instruction Redundancy for
·Sumeet Kumar and Aneesh Aggarwal
A Low-cost Memory Remapping Scheme for Address Bus
Protection
·Lan Gao, Jun Yang, Marek Chrobak, Youtao Zhang, San
Nguyen, and
Hsien-Hsin S. Lee
Efficient Data Protection for Distributed Shared
Memory Multiprocessors
·Brian Rogers,
Track 2 (Session 4): Characterizing
Program Behavior
Wavelet-Based Phase Classification
·Ted Huffmire and Tim Sherwood
Complexity-based Program Phase Analysis and
Classification
·Chang-Burm Cho and Tao Li
Performance Prediction based on Inherent Program
Similarity
·Kenneth Hoste, Aashish Phansalkar, Lieven Eeckhout,
Andy Georges,
Lizy
K. John, and Koen de Bosschere
Deep
Computing in Biology: Challenges and Progress
Hardware Support for Spin Management in Overcommitted
Virtual Machines
·Philip M. Wells, Koushik Chakraborty, and Gurindar
S. Sohi
Testing Implementations of Transactional Memory
·Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi,
Austen McDonald,
Christos Kozyrakis, and Kunle Olukotun
Efficient Emulation of Hardware Prefetchers via
Event-Driven Helper Threading
·Ilya Ganusov and Martin Burtscher
Track 2 (Session 6): Performance
Profiling and Tuning
DEP: Detailed Execution Profile
·Qin Zhao, Joon Edward Sim, Weng-Fai Wong, and Larry
Rudolph
Whole-Program Optimization of Global Variable Layout
·Nathaniel McIntosh, Sandhya Mannarswamy, and Robert
Hundt
Fast, Automatic, Procedure-Level Performance Tuning
· Zhelong Pan
and Rudolf Eigenmann
Reducing Control Overhead in Dataflow
Architectures
·Andrew Petersen, Martha Mercaldi, Steve Swanson,
Andrew Putnam,
Andrew Schwerin, Mark Oskin, and Susan Eggers
Power-efficient Instruction Delivery through Trace
Reuse
·Chengmo Yang and Alex Orailoglu
Branch Predictor Guided Instruction Decoding
·Oliverio J. Santana,
Ayose Falcon, Alex Ramirez, and Mateo Valero
Track 2 (Session 8): Application-Specific Optimizations
Two-level Mapping based Cache Index Selection for
Packet Forwarding Engines
·Kaushik Rajan and R. Govindarajan
Program Generation for the All-Pairs Shortest Path
Problem
·Sung-Chul Han, Franz
Franchetti, and Markus Pueschel
Combining
Analytical and Empirical Approaches in Tuning Matrix Transposition
·Qingda Lu, Sriram Krishnamoorthy, and P. Sadayappan
Wednesday,
September 20
8:30-9:30 Keynote
IV,
David
Kirk, Nvidia: Slides, Abstract
Adaptive Reorder Buffers for SMT Processors
·Joseph Sharkey, Deniz Balkan, and Dmitry Ponomarev
SEED: Scalable, Efficient Enforcement of
Dependences
·Francisco J.
Mesa-Martinez, Michael C. Huang, and Jose Renau
SPARTAN:
Speculative Avoidance of Register Allocations to
Transient Values for Performance and
Energy-Efficiency
·Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, and
Kanad Ghose
Track 2 (Session 10): Dependences
and Register Allocation
Overlapping Dependent Loads with Addressless Preload
·Zhen Yang, Xudong Shi, Feiqi Su, and Jih-Kown Peir
Prematerialization: Reducing Register Pressure for
Free
·Ivan D. Baev, Richard E. Hank, and David H. Gross
An Empirical Evaluation of Chains of Recurrences for
Array Dependence
·J. Birch, R.A. van Engelen, K.A. Gallivan, and Y.
Shou