Bratin Saha*, Ali-Reza Adl-Tabatabai*, Christos Kozyrakis+
*Intel Corporation
+Stanford University

Overview:

With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Thus, applications will need to be concurrent to exploit the additional computing power in a CMP. Today, programmers use lock-based synchronization for concurrency control. Composing software modules written using locks can lead to well-known problems such as deadlock and poor scalability. Transactional memory (TM) provides an alternate concurrency control mechanism that avoids the pitfalls of lock-based synchronization while providing scalability.

This tutorial will give a comprehensive overview of transactional memory, present the current state of the art in transactional memory research, and discuss some open research problems. We will show how transactional memory can avoid the problems of lock-based synchronization such as deadlock, and poor composability. We will discuss how transactional constructs may be added to languages as an alternative to current synchronization constructs. We will present different implementation strategies - from HW transactional memory to SW transactional memory and hybrid approaches. We will show how to integrate transactional memory with other language and runtime features such as garbage collection, and exceptions and how to leverage compiler optimizations. We will also discuss advanced semantic issues such as nesting, and two-phase commit. Finally, we will present some important open research issues.

Duration:

This will be a half-day (4 hour) tutorial.

Target Audience:

People interested in an overview of transactional programming, including its implementation, integration into a language environment, and usage model.

Organizers:

Bratin Saha is a senior staff researcher in the Programming System Lab at Intel Corporation. He is one of the architects for synchronization and locking in the next generation IA-32 processors. He is currently involved in the design and implementation of a highly scalable runtime for multi-core processors. As a part of this he has been looking at language features, such as transational memory, to ease parallel programming.

Ali-Reza Adl-Tabatabai is a principle engineer in the Programming Systems Lab at Intel Corporation. He leads a team developing compilers and scalable runtimes for future Intel Architectures. His current research concentrates on language features supporting parallel programming for future multi-core architectures.

Christos Kozyrakis is an assistant professor of Electrical Engineering & Computer Science at Stanford. His research focuses on architectures, compilers, and programming models for parallel computer systems. He is currently working on transactional memory techniques that can greatly simplify parallel programming for the average developer.