The Fifteenth International Conference on
Parallel Architectures and Compilation Techniques
September 16-20, 2006
For tutorial inquiries, send a note to the Tutorials Chair, Sandhya Dwarkadas (sandhya at cs.rochester.edu).
Saturday, September 16, 2006 Full day workshop
Programming Models for Ubiquitous Parallelism
Organizers:
Sam Midkiff, Purdue, midkiff at purdue.edu
Maria Garzaran, UIUC, garzaran at cs.uiuc.edu
Morning tutorial (half day)
Cell BE Processor Tutorial: Programming Tools and Techniques
Description
Organizer:
Dr. Michael Perrone, IBM Research, mpp at us.ibm.com
Afternoon workshop (half day)
7th MEDEA (MEmory performance:
DEaling with Applications, systems and architecture)
Organizers:
Sandro Bartolini, University of Siena, Italy, bartolini at dii.unisi.it
Pierfrancesco Foglia, University of Pisa, Italy, foglia at iet.unipi.it
Roberto Giorgi, University of Siena, Italy, giorgi at unisi.it
Cosimo Antonio Prete, University of Pisa, Italy, prete at iet.unipi.it
Afternoon tutorial (half day)
A Case Study of a Physically Based Visual Simulation Targeting
Emerging Architectures and Programming Models
Description
Organizer:
Yahya Mirza, Aurora Borealis Software LLC, yahya at aurasoft.net
Sunday, September 17, 2006 Full day workshop
Workshop on Tools and Compilers for Hardware Acceleration (TCHA)
Organizers:
Walid Najjar, University of California Riverside, najjar at cs.ucr.edu
Kathryn O'Brien, IBM TJ Watson Research Center, kmob at us.ibm.com
Morning tutorial (half day, 4 hours)
X10: Concurrent object-oriented programming for modern architectures
Organizers:
Vijay Saraswat, IBM TJ Watson Research Center, vijay at saraswat.org
Christoph von Praun, IBM TJ Watson Research Center, praun at us.ibm.com
Morning tutorial (half day, 4 hours)
IA-32 Execution Layer: Dynamic Binary Translator from IA-32 to Intel
Itanium Architecture
Description
Organizers:
Orna Etzion and Yigal Zemach, Intel Haifa
orna.etzion at intel.com, yigal.zemach at intel.com
Afternoon workshop (half day)
OSIHPA: 2nd International Workshop on Operating System Interference
in High Performance Applications
Organizers:
Ronald Mraz, Owl Computing Technologies, Inc
Fabrizio Petrini, Pacific Northwest National Laboratory
Matt Sottile, Los Alamos National Laboratory
fabrizio.petrini at pnl.gov, matt at lanl.gov, ronmraz at gmail.com
Afternoon tutorial (half day, 4 hours with 2 breaks)
Transactional Programming in a Multi-Core Environment
Description; Tutorial Slides
Organizers:
Bratin Saha*, Ali-Reza Adl-Tabatabai*, Christos Kozyrakis+
*Programming Systems Lab, Intel Corporation; +Stanford University
bratin.saha at intel.com, ali-reza.adl-tabatabai at intel.com
Christos at stanford.edu