The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed atmosphere for exchange of ideas and promotes research in critical subareas of physical design for VLSI systems.

This year's workshop emphasizes deep-submicron and high-performance issues, and also provides a special focus on opportunities in CAD for micro electromechanical systems (MEMS). There are four outstanding panel sessions:

1. future needs and directions for deep-submicron physical design,
2. physical design needs for MEMS,
3. manufacturing and yield issues in physical design, and
4. critical disconnects in design views, data modeling, and back-end flows (e.g., for physical verification).

There are also many outstanding technical paper sessions. Free-flowing discussion will be promoted through the limited workshop attendance, the poster session and the "open commentary" mechanism in each technical session, as well as a concluding open problems session. During the workshop, a benchmarks competition will occur in the areas of netlist partitioning and performance-driven cell placement.

Sunday, April 14

7:00pm-8:30pm: Reception (refreshments provided)

Monday, April 15

8:40am-10:00am: Session 1, Timing-Driven Interconnect Resynthesis

• T. Okamoto and J. Cong (UC Los Angeles), Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion
• J. Lillis, C.-K. Cheng and T.-T. Lin (UC San Diego), Simultaneous Routing and Buffer Insertion for High Performance Interconnect
• L. Entrena, E. Olias and J. Uceda (U. Carlos III of Madrid and U. Politecnica of Madrid), Timing Optimization by Redundancy Addition/Removal
• Open Commentary - Moderators: D. Hill (Synopsys), P. Suaris (Interconnectix)

10:00am-10:20am: Break

10:20am-12:00pm: Session 2, Interconnect Optimization

• C. P. Chen, Y. P. Chen and D. F. Wong (U. Texas Austin), Optimal Wire-Sizing Formula Under Elmore Delay Model
• A. Vittal and M. Marek-Sadowska (UC Santa Barbara), Reducing Coupled Noise During Routing
• J. Cong and L. He (UC Los Angeles), Simultaneous Transistor and Interconnect Sizing Using General Dominance Property
• D. Lehther, S. Pullela, D. Blaauw and S. Ganguly (Somerset Design Center and Motorola), Hierarchical Clock-Network Optimization
• Open Commentary - Moderators: D. Hill (Synopsys), M. Lorenzetti (Mentor)

12:00pm-2:00pm: Lunch
Workshop Keynote Address: Prof. C. L. Liu, U. of Illinois
Algorithmic Aspects of Physical Design of VLSI Circuits

2:00pm-2:45pm: Session 3, A Tutorial Overview of MEMS
Speaker: K. Gabriel (ARPA)

2:45pm-3:00pm: Break

3:00pm-4:15pm: Session 4, Physical Design for MEMS

• Gary K. Fedder and Tamal Mukherjee (Carnegie-Mellon U.), Physical Design for Surface Micromachined MEMS
• R. Mahadevan (MCNC), Physical Design Support for MCNC/MUMPS
• E. Berg, N. Lo and K. Pister (UC Los Angeles), Synthesis and Extraction for MEMS Design

4:15pm-4:30pm: Break

4:30pm-6:00pm: Session 5, Panel: Physical Design Needs for MEMS
Moderator: K. Pister (UC Los Angeles)
Panelists include:

• S. Bart (Analog Devices)
• G. Fedder (Carnegie-Mellon U.)
• K. Gabriel (ARPA)
• I. Getreu (Analogy)
• R. Grafton (NSF)
• R. Mahadevan (MCNC)
• J. Tanner (Tanner Research)

6:00pm-8:00pm: Dinner

8:00pm-9:30pm: Session 6, Panel: Deep-Submicron Physical Design: Future Needs and Directions
Panelists include:

• T. C. Lee (former VP Eng, SVR; President/CEO, Neo Paradigm Labs)
• L. Scheffer (Architect, Cadence)
• W. Vercruysse (UltraSPARC III CAD Manager, Sun)
• M. Wiesel (CAD Manager, Intel)
• T. Yin (VP R&D, Avant!)

Tuesday, April 16

• S. Dutt and W. Y. Deng (U. Minnesota and LSI Logic), VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques
• C. J. Alpert, L. Hagen and A. B. Kahng (UC Los Angeles and Cadence) A Hybrid Multilevel/Genetic Approach for Circuit Partitioning
• J. Hwang and A. El Gamal (Xilinx and Stanford U.), Min-Cut Replication for Delay Reduction
• Open Commentary - Moderators: J. Frankle (Xilinx), L. Scheffer (Cadence)

10:10am-11:50am: Session 8, Topics in Hierarchical Design

• R. Nijssen and J. Jess (TU Eindhoven), Two-Dimensional Datapath Regularity Extraction
• G. Zimmermann (U. Kaiserslautern), Hierarchical Net Length Estimation
• H. Esbensen and E. S. Kuh (UC Berkeley), Exploring the Design Space for Building-Block Placements Considering Area, Aspect Ratio, Path Delay and Routing Congestion
• S. Koakutsu, M. Kang and W. W.-M. Dai (Chiba U. and UC Santa Cruz), Genetic Simulated Annealing and Application to Non-Slicing Floorplan Design
• Open Commentary

11:50pm-1:30pm: Lunch

1:30pm-3:00pm: Session 9, Poster Session

• M. J. Alexander, J. P. Cohoon, J. Colflesh, J. Karro, E. L. Peters and G. Robins (U. of Virginia), Physical Layout for Three-Dimensional FPGAs
• B. Basaran and R. Rutenbar (Carnegie-Mellon U.), Efficient Area Minimization for Dynamic CMOS Circuits
• M. Hossain, B. Thumma and S. Ashtaputre (Compass Design Automation), A Fast Technique for Timing-Driven Placement Re-engineering
• K. Hahn and R. Bruck (U. Dortmund), An Approach to Layout and Process Verification for Microsystem Physical Design
• M. K. Long, J. W. Burdick and T. J. Hubbard (Caltech), Computer Aided Micro-Machining for Wet Etch Fabrication
• I. Peters, P. Molitor and M. Weber (U. Halle and Deuretzbacher Research GmbH), Over-the-Cell Routing with Vertical Floating Pins
• R. Sun, R. Gupta and C. L. Liu (Altera and U. Illinois), Congestion-Balanced Placement for FPGAs
• K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu (UC Santa Barbara and Actel), Fanout Problems in FPGA
• J. Velasco, X. Marin, R. P. Llopis and J. Carrabina (IMB-CNM U. Autonoma de Barcelona, Philips Research Labs Eindhoven), An Optimal Pairing and Chaining Algorithm for Layout Generation
• G. Yee and C. Sechen (U. Washington), Clock-Delayed Domino in Adder and Random Logic Design

3:00pm-4:00pm: Session 10, Manufacturing/Yield Issues I

• K. P. Wang, M. Marek-Sadowska and W. Maly (UC Santa Barbara and Carnegie-Mellon U.), Layout Design for Yield and Reliability
• V. Chiluvuri (Motorola), Yield Optimization in Physical Design (invited survey paper)

4:00pm-4:15pm: Break

4:15pm-5:45pm: Session 11, Panel: Manufacturing/Yield Issues II
Panelists include:

• V. Chiluvuri (Motorola)
• I. Koren (U. Massachusetts Amherst)
• J. Burns (IBM Watson Research Center)
• W. Maly (Carnegie-Mellon U.)

5:45pm-7:30pm: Dinner

7:30pm-9:30pm: Session 12, Panel: Design Views, Data Modeling and Flows: Critical Disconnects
A talk by C. Sechen (U. Washington)

• H.-P. Tseng and C. Sechen (U. Washington), A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph and Tile Expansion Approach
• L.-C. E. Liu and C. Sechen (U. Washington), A Multi-Layer Chip-Level Global Route

• W. W.-M. Dai (UC Santa Cruz, VP Ultima Interconnect Technologies
• L. Jones (Motorola)
• D. Lapotin (IBM Austin Research Center)
• E. Nequist (VP R&D, Cooper & Chyan)
• R. Rohrer (Chief Scientist, Avant!)
• P. Sandborn (VP, Savantage)

Wednesday, April 17

• G. Tellez, D. A. Knol and M. Sarrafzadeh (Northwestern U.) A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven Placement Problems
• J. L. Neves and E. G. Friedman (U. Rochester), Reduced Sensitivity of Clock Skew Scheduling to Technology Variations
• L.-C. E. Liu and C. Sechen (U. Washington), Multi-Layer Pin Assignment for Macro Cell Circuits
• Open Commentary

9:50am-10:10am: Break

10:10am-11:30am: Session 14, Topics in Layout

• S. K. Dong, P. Pan, C. Y. Lo and C. L. Liu (Silicon Graphics, Clarkson U., Lucent, U. Illinois), Constraint Relaxation in Graph-Based Compaction
• B. Basaran and R. Rutenbar (Carnegie-Mellon U.), An O(n) Algorithm for Transistor Stacking with Performance Constraints
• B. Guan and C. Sechen (Silicon Graphics and U. Washington), Efficient Standard Cell Generation When Diffusion Strapping is Required
• Open Commentary - Moderator: A. Domic (Cadence)

11:30am-12:00pm: Session 15, Open Problems
Moderators: A. B. Kahng (UC Los Angeles), B. Preas (Xerox PARC)

12:00pm-2:00pm: Lunch (and benchmark competition results)

2:00pm: Workshop adjourns

Travel and Accommodations

The Sheraton Reston is located at:

Please make your room reservation directly with the Reston Sheraton hotel.

Driving directions from Dulles Airport: take the Washington Dulles Access and Toll Road (route 267) to the Reston Parkway Exit (3). Turn right at the light after paying toll. Take the next left onto Sunrise Valley Drive, and continue for a couple blocks to the Sheraton (on your left).

A block of rooms is being held for the nights of Sunday through Wednesday (April 14 through April 17). Room rates are $95 per night for single occupancy, and $105 per night for double occupancy. The number of rooms available at these rates is limited, and they are only being held through March 24 (so early registration is highly recommended).

The Washington D.C. weather tends to be chilly in April, so warm dress is suggested for the outdoors.

Sightseeing and Attractions

The Smithsonian Institution (telephone (202) 357-2700) operates a number of superb museums that flank the National Mall, including:

• Freer Gallery of Art (Asian and 19th and 20th-century American art)
• Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
• National Air and Space Museum (history of aviation and space exploration)
• National Museum of African Art (collection and study of African art)
• National Museum of American Art (paintings, graphics, and photography)
• National Museum of American History (technology and culture in America)
• National Museum of Natural History (history of the natural world)
• National Portrait Gallery (portraits of distinguished americans)
• National Postal Museum (history of postal communication and philately)
• Sackler Gallery of Asian art (from ancient to present)

Other attractions and tours around the D.C. area include (please call the numbers below for schedules):

• Arlington National Cemetary (703) 697-2131
• Bureau of Engraving and Printing (202) 622-2000
• Congressional buildings (202) 225-6827
• FBI Headquarters (202) 324-3447
• Library of Congress (202) 707-5000
• National Aquarium (202) 482-2825
• National Archives (202) 501-5000
• National Zoological Park (202) 673-4821
• The Pentagon (703) 695-1776
• Supreme Court (202) 479-3030
• Treasury Department (202) 622-2000
• The White House (202) 456-7041

There are a number of reasonably priced eating places on the Mall; the East Wing of National Gallery and the Air and Space Museums offer good food and a place to sit down after sightseeing. Provisions will be made for low-cost transportation to and from the Mall and downtown Washington D.C., so bring your camera and strolling shoes and enjoy our Nation's Capital!

Workshop Organization

General Chair:

Gabriel Robins (University of Virginia)

Steering Committee:

M. Lorenzetti (Mentor Graphics)

B. Preas (Xerox PARC)

Technical Program Committee:

C. K. Cheng (UC San Diego)

J. P. Cohoon (University of Virginia)

J. Cong (UCLA)

A. Domic (Cadence)

J. Frankle (Xilinx)

E. Friedman (University of Rochester)

D. Hill (Synopsys)

L. Jones (Motorola)

A. B. Kahng (UCLA, Chair)

Y.-L. Lin (Tsing Hua)

K. Pister (UCLA)

M. Marek-Sadowska (UC Santa Barbara)

C. Sechen (University of Washington)

R.-S. Tsay (Arcsys)

G. Zimmermann (University of Kaiserslautern)

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                Registration Fees (Includes All Meals)

              Advance (Through April 1)  Late (After April 1/On-Site)
ACM Members         __ $355                      __ $440
Non-ACM             __ $455                      __ $540
Students            __ $250                      __ $250

         ACM Membership Number: _____________________________

         Dietary restrictions, if any: ______________________

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