References

  1. M. J. Alexander, J. P. Cohoon, J. L. Ganley, and G. Robins, An Architecture-Independent Approach to FPGA Routing Based on Multi-Weighted Graphs, in Proc. European Design Automation Conf., Grenoble, France, September 1994, pp. 259-264.

  2. M. J. Alexander and G. Robins, A New Approach to FPGA Routing Based on Multi-Weighted Graphs, in Proc. ACM/SIGDA Intl. Workshop on Field-Programmable Gate Arrays, Berkeley, CA, February 1994.

  3. S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, Boston, MA, 1992.

  4. Y.-W. Chang, S. Thakur, K. Zhu, and D. F. Wong, A New Global Routing Algorithm for FPGAs, in Proc. IEEE Intl. Conf. Computer-Aided Design, San Jose, CA, November 1994.

  5. J. Cong, K. S. Leung, and D. Zhou, Performance-Driven Interconnect Design Based on Distributed RC Delay Model, in Proc. ACM/IEEE Design Automation Conf., Dallas, June 1993, pp. 606-611.

  6. E. W. Dijkstra, A Note on Two Problems in Connection With Graphs, Numerische Mathematik, 1 (1959), pp. 269-271.

  7. J. L. Ganley, private communication, April, 1994.

  8. J. Griffith, G. Robins, J. S. Salowe, and T. Zhang, Closing the Gap: Near-Optimal Steiner Trees in Polynomial Time, IEEE Trans. Computer-Aided Design, 13 (1994), pp. 1351-1365.

  9. F. K. Hwang, D. S. Richards, and P. Winter, The Steiner Tree Problem, North-Holland, 1992.

  10. A. B. Kahng and G. Robins, A New Class of Iterative Steiner Tree Heuristics With Good Performance, IEEE Trans. Computer-Aided Design, 11 (1992), pp. 893-902.

  11. A. B. Kahng and G. Robins, On Optimal Interconnections for VLSI, Kluwer Academic Publishers, Boston, MA, 1995. [here is the table-of-contents and intro of this book]

  12. L. Kou, G. Markowsky, and L. Berman, A Fast Algorithm for Steiner Trees, Acta Informatica, 15 (1981), pp. 141-145.

  13. G. G. Lemieux and S. D. Brown, A Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays, in Proc. ACM/SIGDA Physical Design Workshop, Lake Arrowhead, CA, April 1993.

  14. S. K. Rao, P. Sadayappan, F. K. Hwang, and P. W. Shor, The Rectilinear Steiner Arborescence Problem, Algorithmica, (1992), pp. 277-288.

  15. Y. Sun, T. C. Wang, C. K. Wong, and C. L. Liu, Routing for Symmetric FPGAs and FPICs, in Proc. IEEE Intl. Conf. Computer-Aided Design, Santa Clara, CA, November 1993, pp. 486-490.

  16. S. M. Trimberger, Field-Programmable Gate Array Technology, S. M. Trimberger, editor, Kluwer Academic Publishers, Boston, MA, 1994.

  17. Y.-L. Wu and D. Chang, On the NP-Completeness of Regular 2-D FPGA Routing Architectures and a Novel Solution, in Proc. IEEE Intl. Conf. Computer-Aided Design, San Jose, CA, November 1994, pp. 362-366.

  18. Y.-L. Wu and M. Marek-Sadowska, An Efficient Router for 2-D Field Programmable Gate Arrays, in European Design and Test Conf., 1994, pp. 412-416.

  19. Xilinx, The Programmable Gate Array Data Book, Xilinx, Inc., San Jose, California, 1994.

  20. A. Z. Zelikovsky, An 11/6 Approximation Algorithm for the Network Steiner Problem, Algorithmica, 9 (1993), pp. 463-470.