This paper was awarded the Bob Rau memorial award for best student paper!
M.R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, and S. Velusamy.
In Microelectronics Journal: Circuits and Systems, Elsevier.
Abstract
This paper describes a thermal-modeling approach that is easy to use and computationally
efficient for modeling thermal effects and thermal-management techniques at the processor
architecture level. Our approach is based on modeling thermal behavior of the microprocessor
die and its package as a circuit of thermal resistances and capacitances that correspond
to functional blocks at the architecture level. This yields a simple compact model,
yet heat dissipation within all major functional blocks and the heat flow among blocks and
through the package are accounted for. The model is parameterized, boundary- and initialconditions
independent, and is derived by a structure assembly approach. The architecture
community has demonstrated growing interest in thermal management, but currently lacks
a way to model on-chip temperatures in a tractable way. Our model can be used for initial
exploration of the design space at the architecture level. The model can easily be integrated
into popular power/performance simulators, can be used to determine how thermal stress is
correlated to the architecture, and how architecture-level design decisions influence thermal
behavior and related effects.
The work presented in this paper has since been partially superseded by:
This paper was awarded the Bob Rau memorial award for best student paper!