K. Skadron, Mircea Stan, Marco Barcella, Amar Dwarka, Wei Huang, Yingmin Li, Yong Ma, Amit Naidu, Dharmesh Parikh, Paolo Re, Garrett Rose, Karthik Sankaranarayanan, Ram Suryanarayan, Sivakumar Velusamy, Hao Zhang, Yan Zhang
In Proceedings of the 2002 International Workshop on THERMal Investigations of ICs and Systems (THERMINIC), Madrid, Spain, Oct. 2002.
This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach models thermal behavior of the die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple model that still accounts for heating in individual architecture-level blocks, while also capturing heat flow among blocks and through the package. A model like this that can be integrated with cycle-level microarchitecture simulators is needed, because the architecture community has demonstrated growing interest in thermal management, but currently lacks any way to model on-chip temperatures in a tractable way.