Fall 2001 CS 654 Assignment 3 FAQ

  1. Do cache writes really take 0 cycles?
  2. Why doesn't bpred_lookup() always return address?
  3. What are the various penalties for misprediction?
  4. If a branch is mispredicted, when do I start fetching from the correct PC?
  5. Say the instruction cache is suffering a miss penalty, can I probe the data cache? (and variants)
  6. What about stalling? When should that occur?
  7. I go to sim-pipe.h and I try to set:
    static int mem_lat[2] =
    { /* lat to first chunk */10, /* lat between remaining chunks */0 };
    But then I get an error. What's going on?
  8. If there is a misprediction of the branch, and if there is a cache miss in for the fetch of the mispredicted instruction... should this be modeled?