Fall 2001 CS 654 Assignment 3 FAQ

Do cache writes really take 0 cycles?

• No, I misspoke when I said that. Cache writes may also suffer a miss penalty.

Why doesn't bpred_lookup() always return address?

• bpred_lookup() probes the BTB as well, if it misses in the BTB it will merely provide a direction prediction
• if only a direction prediction is provided, the values correspond as follows:
  0: not taken (PC+4) 1: taken (branch target address)

What are the various penalties for misprediction?

• Predict Taken - Actually Taken: 1 cycle
• Predict Taken - Actually Not Taken: 2 cycles
• Predict Not Taken - Actually Taken: 2 cycles
• Predict Not Taken - Actually Not Taken: 0 cycles

If a branch is mispredicted, when do I start fetching from the correct PC?

• See above, the penalty for mispredictions is 2 cycles in this pipeline. Fetching of the correct PC should begin as soon as IF becomes available after the branch that was mispredicted has resolved (after the branch completes EX).
• If there is a misprediction and there is an overlapping instruction cache miss, wait for the instruction cache miss to complete.

Say the instruction cache is suffering a miss penalty, can I probe the data cache? (and variants)

• Data cache and instruction cache are separate in this assignment.
• Therefore, if the instruction cache is suffering a miss, if there is an instruction further down in the pipeline that needs to probe the data cache, it may do so.
• If the data cache is suffering a miss, it depends. The cycle in which the miss is first realized, the instruction cache may be probed, but subsequent cycles until the data cache miss is resolved, the i-cache can't be probed. This is because the data cache miss is preventing forward movement of the instructions.

What about stalling? When should that occur?

• Instruction cache misses
• Data cache misses
• Branch mispredictions (flush the necessary parts of the pipeline)
• Hazards that can't be handled by forwarding. I.e., loads that haven't reached the MEM stage yet.

I go to sim-pipe.h and I try to set:
static int mem_lat[2] =
{ /* lat to first chunk */10, /* lat between remaining chunks */0 };
But then I get an error. What's going on?

• Check for the following line in your sim_check_options():
  if (mem_lat[0] < 1 || mem_lat[1] < 1)
  fatal("all memory access latencies must be greater than zero");
  

  The line above requires that both latencies be set to a value > 0. For this assignment we want to allow mem_lat[1] to be 0, so relax the second half and just check that mem_lat[1]<0 (negative).

If there is a misprediction of the branch, and if there is a cache miss in for the fetch of the mispredicted instruction... should this be modeled?

• Yes, the output files are incorrect in not properly fetching the mispredicted instruction and suffering the instruction cache miss.
• It's not very likely that I will get a chance to fix this before Monday.