Advanced Computer Architecture

Review Assignments

Review 1

Due Jan 23, 2019

Onur Mutlu, "Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions", Invited Article, 2018

Richard Hamming, "You and Your Research"

Review 2 (any two)

Due Jan 30, 2019

Dennis and Misunas, “A preliminary architecture for a basic data flow processor,” ISCA 1974.

Arvind and Nikhil, "Executing a program on the MIT tagged-token dataflow architecture," IEEE TC 1990.

Kung, H. T., "Why Systolic Architectures?", IEEE Computer 1982.

Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. S.," Warp architecture and implementation", ISCA 1986.

Review 3

Due Feb 6, 2019

Esmaeilzadeh et al., "Dark silicon and the end of multicore scaling", ISCA 2011.

Y.-H. Chen et al., “Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks,” ISCA 2016.

Review 4

Due Mar 4, 2019

Chen et a;., "TVM: An Automated End-to-End Optimizing Compiler for Deep Learning", OSDI 2018.

Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit", ISCA 2017.

Review 5

Due Mar 18, 2019

Kwon et al., "Beyond the Memory Wall: A Case for Memory-centric HPC System for Deep Learning", MICRO 2018.

Han et al., "EIE: Efficient Inference Engine on Compressed Deep Neural Network", ISCA 2016.

Review 6

Due Apr 1, 2019

Gao et al., TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory, ASPLOS 2017.

Parashar et al., SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks, ISCA 2017.

Review 7

Due Apr 8, 2019

Li et al., Scaling Distributed Machine Learning with the Parameter Server, OSDI 2014.

Shafiee et al., ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016.

Review 8

Due Apr 24, 2019

Bonawitz et al., Towards Federated Learning at Scale: System Design, ArXiv 2019.

Abadi et al., TensorFlow: A System for Large-Scale Machine Learning, OSDI 2016.