2017

Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content
Samira Khan, Chris Wilkerson, Zhe Wang, Alaa Alameldeen, Donghyuk Lee, and Onur Mutlu
International Symposium on Microarchitecture (MICRO)
Boston, USA, October 2017.
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Donghyuk Lee, Samira Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, and Onur Mutlu
International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS)
Champaign-Urbana, Illinois, USA, June 2017.
Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures
Jack Wadden, Samira Khan, Kevin Skadron
25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Napa, CA, USA, April. 2017
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan, Nandita Vijaykumar, Samira Khan, , Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu
23rd International Symposium on High-Performance Computer Architecture (HPCA)
Austin, TX, USA, February 2017.

2016

A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM
Samira Khan, Chris Wilkerson, Donghyuk Lee, Alaa R. Alameldeen, and Onur Mutlu
IEEE Computer Architecture Letters (CAL)
November 2016. [pdf]
Zorua: A Holistic Approach to Resource Virtualization in GPUs
Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Khan, Ashish Shrestha, Saugata Ghose, Adwait Jog, Phillip B. Gibbons, and
Onur Mutlu
49th International Symposium on Microarchitecture (MICRO)
Taipei, Taiwan, October 2016. [pdf]
Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and Onur Mutlu
34th IEEE International Conference on Computer Design (ICCD)
Phoenix, AZ, USA, October 2016. [pdf]
PARBOR: An Efficient System-Level Technique to Detect Data Dependent Failures in DRAM
Samira Khan,  Donghyuk Lee, and Onur Mutlu
International Conference on Dependable Systems and Networks (DSN)
France, June 2016. [pdf] [slides]
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Kevin Hsieh, Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Tianshi Li,   Samira Khan,  and Onur Mutlu
International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS)
France, June 2016. [pdf] [slides]
Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost
Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko,  Samira Khan,  and Onur Mutlu
ACM Transactions on Architecture and Code Optimization (TACO), Vol. 12, January 2016
Presented at the 11th HiPEAC Conference, Prague, Czech Republic, January 2016. [pdf] [slides]

2015

Dual-Scheme Checkpointing: A Software-Transparent Mechanism for Supporting Crash Consistency in Persistent Memory Systems
Jinglei Ren, Jishen Zhao,  Samira Khan,  Jongmoo Choi, Yongwei Wu, and Onur Mutlu
48th International Symposium on Microarchitecture (MICRO)
Waikiki, Hawaii, USA, December 2015. [pdf] [slides]
The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-Application Interference at Shared Caches and Main Memory
Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh,  Samira Khan,  and Onur Mutlu
48th International Symposium on Microarchitecture (MICRO)
Waikiki, Hawaii, USA, December 2015. [pdf] [slides]
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
Moinuddin Qureshi, Dae Hyun Kim,  Samira Khan,  Prashant Nair, and Onur Mutlu
45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
Rio de Janeiro, Brazil, June 2015.   [pdf]
Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko,  Samira Khan,  Vivek Seshadri, Kevin Chang, and Onur Mutlu
21st International Symposium on High Performance Computer Architecture (HPCA)
San Francisco, CA, February 2015.   [pdf] [slides] [data set]

2014

The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study
Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu
ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS)
Austin, Texas, June 2014.   [pdf] [slides] [data set]
Last-level Cache Deduplication
Yingying Tian, Samira Khan, Daniel Jimenez, and Gabriel Loh:
International Conference on Supercomputing, (ICS)
Muenchen, Germany, June 2014.  [pdf]
Improving Cache Performance by Exploiting Read-Write Disparity
Samira Khan,  Alaa Alameldeen, Chris Wilkerson, Onur Mutlu, and Daniel Jimenez
20th International Symposium on High Performance Computer Architecture (HPCA)
Orlando, Florida, February 2014.  [pdf] [slides]
Best Paper Session

2013

Temporal-based Multilevel Correlating Inclusive Cache Replacement
Yingying Tian, Samira Khan, and Daniel Jimenez
ACM Transactions on Architecture and Code Optimization (TACO)
December 2013.   [pdf]
A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory
Justin Meza, Yixin Luo,   Samira Khan,   Jishen Zhao, Yuan Xie, and Onur Mutlu
5th Workshop on Energy-Efficient Design (WEED)
Tel-Aviv, Israel, June 2013.  [pdf] [slides]
Improving Memory Reliability, Power and Performance Using Mixed-Cell Designs
Alaa Alameldeen, Nam Sung Kim,   Samira Khan,   Hamid Reza Ghasemi, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jimenez
Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May 2013.    [pdf]
Improving Multi-Core Performance Using Mixed-Cell Cache Architecture
Samira Khan, Alaa Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jimenez
19th International Symposium on High Performance Computer Architecture (HPCA)
Shenzhen, China, February 2013.   [pdf] [slides]

2012

Improving Writeback Efficiency with Decoupled Last Write Prediction
Zhe Wang,   Samira Khan,  and Daniel A. Jimenez
19th International Symposium on Computer Architecture (ISCA)
Portland, Oregon, June 2012.  [pdf]
Rank Idle Time Prediction Driven Last-Level Cache Writeback
Zhe Wang,  Samira Khan,   and Daniel A. Jimenez
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC)
Beijing, China, June 2012.   [pdf]
Decoupled Dynamic Cache Segmentation
Samira Khan, Zhe Wang, and Daniel A. Jimenez
18th International Symposium on High Performance Computer Architecture (HPCA)
New Orleans, Louisiana, February 2012.   [pdf] [slides]

2010

Sampling Dead Block Prediction Last-Level Caches
Samira Khan, Yingying Tian, and Daniel A. Jimenez
43rd International Symposium on Microarchitecture (MICRO)
Atlanta, Georgia, December 2010.   [pdf] [slides]
Insertion Policy Selection Using Decision Tree Analysis
Samira Khan, and Daniel A. Jimenez
28th International Conference of Computer Design (ICCD)
Amsterdam, Netherlands, October 2010.   [pdf]
Using Dead Blocks as a Virtual Victim Cache
Samira Khan, Daniel A. Jimenez, Doug Burger, and Babak Falsafi
19th International Conference on Parallel Architectures and Compilation Techniques (PACT)
Vienna, Austria, September 2010.   [pdf]