The Spring System Description Language (SDL) describes the intended target architecture and other details of the actual implementation layout. This helps with the dilemma of combining abstraction and detailed timing analysis. SDL is implemented as a component of the overall Spring system and is also used as an aid in linking and loading the system.
Fault Tolerant Entities in Real-Time (FERT) is a notation for specifying fault tolerance in adaptive real-time systems. This allows designers to express application-specific reliability and performance requirements.
The Spring real-time scheduling simulator supports the study of various real-time scheduling algorithms. This simulator integrates with the flexible manufacturing research being done in the CARTS lab at the University of Masachusetts. This is a multi-level scheduling simulator that deals with resources at two levels of abstraction (at the high level: products to manufacture, raw materials, etc. and at the low level: computational and data resources) and their linkage.
Real-Time Active Database Experimental Simulator (RADEx) is a real-time, active, temporal database simulator. It supports research on time cognizant concurrency control protocols, real-time transaction scheduling, and real-time logging and recovery.
Spring C extends the C programming language to include constructs such as bounded loops and resource reservations. The compiler analyzes source code to locate blocking points and efficiently decomposes processes into schedulable entities called tasks. The worst case execution time for each task is automatically computed. Programmers can specify deadline and other information needed for real-time computing. The compiler works closely with SDL.
A protoype run-time system for Real-Time Concurrent C (RTCC) has been built as an extension of ATT's Concurrent C. This prototype allows constructs that specify hard real-time computations and provide for various types of guarantee.
Current work on tools includes enhancing both the SDL notation for the Spring environment and the FERT notation as part of a joint effort with 2 European groups: CNR in Pisa, Italy and York, Univ., England.
Enhancing both the Spring scheduling simulator and the RADEx simulator top the list of current work in this area. Other interests include making these simulators accessible via NII (the information superhighway). A new design tool for multi-level design of embedded real-time systems called EMBED WEB has been designed.