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2005 Papers:
  • Y. Sazeides, R. Kumar, D. M. Tullsen, T. Constantinou. "The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best." Volume 4, Jan. 2005. [Go to IEEE Xplore]
  • O. Mutlu, H. Kim, J. Stark, Y. N. Patt. "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor." Volume 4, Jan. 2005. [Go to IEEE Xplore]
  • C. Zhang. "Balanced Instruction Cache: Reducing Conflict Misses of Direct-Mapped Caches through Balanced Subarray Accesses." Volume 4, May. 2005. [Go to IEEE Xplore]
  • G. Ottoni, R. Rangan, A. Stoler, M. J. Bridges, D. I. August. "From Sequential Programs to Concurrent Threads." Volume 4, Jun. 2005. [Go to IEEE Xplore]
  • A. K. Gupta, W. J. Dally. "Topology Optimization of Interconnection Networks." Volume 4, Jul. 2005. [Go to IEEE Xplore]
  • T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, E. Ayguadé. "Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors." Volume 4, Jul. 2005. [Go to IEEE Xplore]
  • N. Riley, C. Zilles. "Probabilistic Counter Updates for Predictor Hysteresis and Bias." Volume 4, Aug. 2005. [Go to IEEE Xplore]
  • H. Zhou. "A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors." Volume 4, Sep. 2005. [Go to IEEE Xplore]
  • M.-S. Lee, S.-K. Lee, J. Lee, S.-R. Maeng. "Adopting System Call Based Address Translation into User-Level Communication." Volume 4, Sep. 2005. [Go to IEEE Xplore]
  • J. H. Ahn, W. J. Dally. "Data Parallel Address Architecture." Volume 4, Oct. 2005. [Go to IEEE Xplore]

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