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2008 Papers:
  • B. Lin and R. Sunkam Ramanujam. "Weighted Random Routing on Torus Networks." Computer Architecture Letters, vol. 7, Nov. 2008, DOI 10.1109/L-CA.2008.14. [Go to IEEE Xplore]
  • J. Ahn, J. Leverich, R. Schreiber, and N. Jouppi. "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs." Computer Architecture Letters, vol. 7, Nov. 2008, DOI 10.1109/L-CA.2008.13. [Go to IEEE Xplore]
  • A. Golander, S. Weiss, and R. Ronen. "DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals." Computer Architecture Letters, vol. 7, July 2008. [Go to IEEE Xplore]
  • I. Walter, I. Cidon, and A. Kolodny. "BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP." Computer Architecture Letters, vol. 7, July 2008. [Go to IEEE Xplore]
  • S. Fide and S. Jenks. "Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors." Computer Architecture Letters, vol. 7, July 2008. [Go to IEEE Xplore]
  • C. Gomez Requena, F. Gilabert Villamon, M. Gomez, P. Lopez, and J. Duato. "Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • Z. Li, C. Zhu, L. Shang, R. Dick, and Y. Sun. "Transaction-Aware Network-on-Chip Resource Reservation." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • D. Pao, W. Lin, and B. Liu. "Pipelined Architecture for Multi-String Matching." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • D. Black-Shaffer, J. Balfour, W. Dally, V. Parikh, and J. Park. "Hierarchical Instruction Register Organization." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • J. Lee and X. Xiao. "A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • R. Sunkam Ramanujam and B. Lin. "Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks." Computer Architecture Letters, vol. 7, June 2008. [Go to IEEE Xplore]
  • J. Balfour, W. J. Dally, D. Black-Schaffer, V. Parikh, and J. Park. "An Energy-Efficient Processor Architecture for Embedded Systems." Computer Architecture Letters, vol. 7, Mar. 2008. [Go to IEEE Xplore]

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