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• J. Xin and R. Joseph. "Exploiting Locality to Improve Circuit-level Timing Speculation." Computer Architecture Letters, vol. 8, Oct. 2009, DOI 10.1109/L-CA.2009.50
• A. Sudarsanam, R. Kallam, and A. Dasu. "PRR-PRR Dynamic Relocation." Computer Architecture Letters, vol. 8, Oct. 2009, DOI 10.1109/L-CA.2009.49
• E. Musoll. "A Process-Variation Aware Technique for Tile-Based, Massive Multi-Core Processors." Computer Architecture Letters, vol. 8, Aug. 2009, DOI 10.1109/L-CA.2009.48
• A. Baldassin, F. Klein, G. Araujo, R. Azevedo, and P. Centoducatte. "Characterizing the Energy Consumption of Software Transactional Memory." Computer Architecture Letters, vol. 8, Aug. 2009, DOI 10.1109/L-CA.2009.47
• J. Leverich, M. Monchiero, V. Talwar, P. Ranganathan, and C. Kozyrakis. "Power Management of Datacenter Workloads Using Per-Core Power Gating." Computer Architecture Letters, vol. 8, Aug. 2009, DOI 10.1109/L-CA.2009.46
• D. Chiou, H. Angepat, N. Patil, and D. Sunwoo. "Accurate Functional-First Multicore Simulators." Computer Architecture Letters, vol. 8, July 2009, DOI 10.1109/L-CA.2009.44
• J. Balfour, R. C. Harting, and W. J. Dally. "Operand Registers and Explicit Operand Forwarding." Computer Architecture Letters, vol. 8, July 2009, DOI 10.1109/L-CA.2009.45
• A. Desai and J. Singh. "Architecture Independent Characterization of Embedded Java Workloads." Computer Architecture Letters, vol. 8, May 2009, DOI 10.1109/L-CA.2009.7
• E. Antelo. "A Comment on 'Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network.'" Computer Architecture Letters, vol. 8, May 2009, DOI 10.1109/L-CA.2009.6
• V. Soteriou, R. S. Ramanujam, B. Lin, and L.-S. Peh. "A High-Throughput Distributed Shared-Buffer NoC Router." Computer Architecture Letters, vol. 8, Apr. 2009, DOI 10.1109/L-CA.2009.5
• Z. Guz, E. Bolotin, I. Keidar, a. kolodny, A. Mendelson, and U. Weiser. "Many-Core vs. Many-Thread Machines: Stay Away From the Valley." Computer Architecture Letters, vol. 8, Apr. 2009, DOI 10.1109/L-CA.2009.4
• C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. "CPU Accounting in CMP Processors." Computer Architecture Letters, vol. 8, Apr. 2009, DOI 10.1109/L-CA.2009.3
• C. Barnes, P. Vaidya, and J. Lee. "An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators." Computer Architecture Letters, vol. 8, Apr. 2009, DOI 10.1109/L-CA.2009.2
• P. Wang, Y. Chen, C. Yang, and Y. Cheng. "A Predictive Shutdown Technique for GPU Shader Processors." Computer Architecture Letters, vol. 8, Jan. 2009, DOI 10.1109/L-CA.2009.1.