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• M. Zhang, A. Lebeck, D. Sorin, "Fractal Consistency: Architecting the Memory System to Facilitate Verification," IEEE Computer Architecture Letters, November 2010. DOI 10.1109/L-CA.2010.18.
• R. Manevich, I. Cidon, a. kolodny, I. Walter, "Centralized Adaptive Routing for NoCs," IEEE Computer Architecture Letters, November 2010. DOI 10.1109/L-CA.2010.17.
• M. Lyons, M. Hempstead, G-Y. Wei, D. Brooks, "The Accelerator Store framework for high-performance, low-power accelerator-based systems," IEEE Computer Architecture Letters, November 2010. DOI 10.1109/L-CA.2010.16.
• Z. Fang, E. Hallnor, B. Li, M. Leddige, S.E. Lee, D. Dai, S. Makineni, "Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact", IEEE Computer Architecture Letters, October 2010. DOI 10.1109/L-CA.2010.15.
• S.M.Z. Iqbal, Y. Liang, H. Grahn, "ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems," IEEE Computer Architecture Letters, August 2010, DOI 10.1109/L-CA.2010.14.
• E. Krimer, R. Pawlowski, M. Erez, P. Chiang, "Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.5.
• H. Kim, P. Gratz, "Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.9.
• A. Hilton, A. Roth, "SMT-Directory: Efficient Load-Load Ordering for SMT," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.8.
• M. Hammoud, S. Cho, R. Melhem, "A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.7.
• G. Hoang, C. Bae, J. Lange, L. Zhang, P. Dinda, R. Joseph, "A Case for Alternative Nested Paging Models for Virtualized Systems," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.6.
• F. Petrini, V. Agarwal, D. Pasetto, "Intra-Socket and Inter-Socket Communication in Multi-core Systems," IEEE Computer Architecture Letters, May 2010, DOI 10.1109/L-CA.2010.4.
• S. Park, E. Seo, J. Shin, S. Maeng, J. Lee, "Exploiting Internal Parallelism of Flash-based SSDs," Computer Architecture Letters, February 2010, DOI 10.1109/L-CA.2010.3
• A. Seznec, "A Phase Change Memory as a Secure Main Memory," IEEE Computer Architecture Letters, February 2010, DOI 10.1109/L-CA.2010.2.
• S. Patil and D.J. Lilja, "Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics", IEEE Computer Architecture Letters, vol. 12, January 2010, DOI 10.1109/L-CA.2010.1.