Research Interests

Computer Architecture, VLSI Circuit design

Advisor: Dr. Sudhanva Gurumurthi

Publication

Journals:

1. T. Siddiqua, S. Gurumurthi, "Enhancing NBTI Recovery in SRAM Arrays through Recovery Boosting", IEEE Transactions on Very Large Scale Integration Systems, 2011 (Accepted).

Conferences and Refereed Workshops:

1. T. Siddiqua, S. Gurumurthi and M. R. Stan, “Modeling and Analyzing NBTI in the Presence of Process Variation", International Symposium on Quality Electronic Design, March 2011.
2. V. Mohan, T. Siddiqua, S. Gurumurthi and M. R. Stan, "How I Learned to Stop Worrying and Love Flash Endurance", 2nd Workshop on Hot Topics in Storage and File Systems (HotStorage), Co-located with USENIX Annual Technical Conference, June 2010.
3. T. Siddiqua, S. Gurumurthi, "Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays", IEEE Computer Society Annual Symposium on VLSI, July 2010. (Acceptance Rate=33%)
4. T. Siddiqua, S. Gurumurthi, "A Multi-Level Approach to Reduce the Impact of NBTI on Processor Functional Units", Great Lakes Symposium on VLSI, May 2010. (Acceptance Rate=18%)
5. T. Siddiqua, S. Gurumurthi, "Dynamic NBTI Management in Multicore Processor", Grace Hopper Celebration, ACM Student Research Competition, September 2009.
6. T. Siddiqua, "Balancing Soft Error Coverage with Lifetime Reliability in Redundantly Multithreaded Processors", MS Thesis , September 2009.
7. T. Siddiqua, S. Gurumurthi, "Balancing Soft Error Coverage with Lifetime Reliability in Redundantly Multithreaded Processors", International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems , September 2009. (Acceptance Rate=20%)
8. T. Siddiqua, S. Gurumurthi, "NBTI-Aware Dynamic Instruction Scheduling",
IEEE Workshop on Silicon Errors in Logic - System Effects, March 2009.

Posters:

1. "Dynamic NBTI Management in Multicore Processor", Grace Hopper Celebration, ACM Student Research Competition, September 2009.
2. "NBTI-Aware Dynamic Instruction Scheduling", CRA-W Grad Cohort, March 2009.
3. "NBTI-Aware Dynamic Instruction Scheduling", SELSE, March 2009.
4. "Reliability Adaptive Computer Architecture", CRA-W/CDC PLOSA Workshop, March 2009.
5. "Reliability Adaptive Computer Architecture", UVa Computer Science Day Celebration, February 2009.

Awards

1. Spontaneous Recognition Award, Intel, 2011.
2. Cyber Physical Systems Summer School Scholarship, Georgia Institute of Tech, 2010.
3. GLSVLSI Student Travel Grant, May 2010.
4. SRC 1st Place Winner, Grace Hopper Conference
5. Grace Hopper Scholarship from Sun Microsystem for Hardware Research, 2009
6. ACM Student Research Competition (SRC) Award, September 2009.
7. ISCA Student Travel Grant, June 2009.
8. Grad Cohort Travel Grant, March 2009.
9. CRA-W PLOSA Travel Grant, March 2009.

Reviews

1. Design Automation Conference (DAC), 2011, 2012
2. IEEE International Symponsium on Circuits and Systems (ISCAS), 2012.
3. IEEE Transactions on Computers (TC), 2011
4. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2011
5. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011
6. International Conference of Computer Aided Design (ICCAD), 2009
7. Computer Architecture Letters (CAL), 2010.