Welcome!

My name is Wei Huang. I am now with IBM Research--Austin, doing research on power-aware processors, servers and datacenters.

My current IBM page is here.


I was a postdoctoral researcher in Computer Science at University of Virginia from 2007 to 2009.
I received my PhD in Electrical Engineering from U.Va. in January 2007.

I am working with Prof. Mircea Stan (ECE, thesis advisor) and Prof. Kevin Skadron (CS, thesis co-advisor).

My research interests span the broad areas of computer architecture and integrated circuits. My current research mainly focuses on physically-constrained computer architecture and VLSI—especially chip-level thermal analysis and temperature-aware and power-aware design. I am the primary developer of HotSpot thermal modeling tool that has been quite successfully used in both academia and industry. I am also currently the moderator of HotLeakage. I received a Best Student Paper Award at ISCA 2003, a Winner's Award at the System-on-Chip (SoC) Design Challenge sponsored by SRC in 2006, and an Honorable Mention at ISSCC/DAC Student Design Contest in 2003. I have also taken initial steps in my research to address other challenges posed by the continuous semiconductor technology scaling—the power wall, process and environment variations, reliability issues, 3D integration, and multicores/manycores with the associated on-chip network.

Specifically, I am interested in pursuing the following topics in the near future:
  1. Power, thermal, reliability and performance analysis for novel computer architectures.
  2. Impacts of 3D integration on circuits and architecture, such as integrated DRAM; interchip capacitively-coupled side I/Os; heat removal and power delivery challenges in 3D chips; 3D chip testing and probing techniques.
  3. Reliability-aware design with the aid of reliability sensors for electromigration, NBTI, thermal gradient and thermal cycling, etc. 3D integration poses more reliability challenges.
  4. Manycore processors scaling trend in the contexts of thermal, power delivery and reliability for 2D and 3D.
  5. Extend HotSpot thermal modeling methodology to higher levels of abstraction (box, rack and system levels) for better energy and thermal management at various levels of interest.


My CV is here.

         

          Chips


        1. Analog Turbo Decoder in SiGe BiCMOS (Honorable Mention in ISSCC/DAC Student Design Contest in 2003)


        2. An SRAD Image Processor as a Reconfigurable, Temperature-Aware SoC Designed for Low-Power Operation (First
        Place Winner in Phase I, Second Place Winner in Phase II of SRC SoC Design Challenge, 2005-2006).
             - Phase I report
             - Phase II report
             - Poster at SRC Symposium, 2006
             - Memory generator paper at CDNLive! 2006


      Major Projects

  1. HotSpot thermal modeling tool for architects.
  2. Manycore power and thermal scaling trends for 2D and 3D integration, and their implications for computer architects
  3. Interconnect self-heating analysis and modeling; Electromigration model and reliability-aware design.
  4. Thermal and leakage characterization of IBM POWER5 (during internship at IBM Research)
  5. Analog Turbo Decoder in SiGe BiCMOS
  6. System-on-chip (SoC) implementation of Speckle Reduction Anisotropic Diffusion (SRAD), an ultrasound image enhancement algorithm.


       Recent papers

        1. W. Huang, K. Skadron, S. Gurumurthi, R. Ribando and M. Stan. “A Coarse Exploration of Temperature-Aware Manycore Design with Amdahl’s Law”, submitted for review in 2009.  (pdf)

        2. W. Huang
, K. Skadron, S. Gurumurthi, R. Ribando and M. Stan. “
Differetiating the Roles of IR Measurement and Simulation
for Power and Temperature-Aware Design”, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2009. (pdf)

        3. W. Huang
, M. Stan, K. Sankaranarayanan, R. Ribando and K. Skadron. “Many-Core Design from a Thermal
Perspective”, Design Automation Conference (DAC), June 2008. (pdf)


    Full List of Publications

JOURNAL PAPERS

1. W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan, “Accurate, Pre-RTL Temperature-Aware Processor Design Using a Parameterized, Geometric Thermal Model”, IEEE Transactions on Computers(TCOMP), September, 2008. (pdf)

2. Z. Lu, W. Huang, K. Skadron, J. Lach and M. R. Stan. “Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications”, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), February, 2007. (pdf)

3. W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron and M. R. Stan. “HotSpot: Thermal Modeling for CMOS VLSI Systems”, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), May 2006. (pdf)

4. W. Huang, M. R. Stan and K. Skadron. “Parameterized Physical Compact Thermal Modeling”, IEEE Transactions on Component and Packaging Technologies (TCAPT), December, 2005. (pdf)

5. K Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-aware computer systems: opportunities and challenges”, IEEE Micro Magazine, Nov-Dec. 2003. (pdf)

6. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, D. Tarjan, “Temperature-Aware Microarchitecture: modeling and implementation”, ACM Transactions on Architecture and Code Optimization (TACO), March 2004. (pdf)

7. M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, S. Velusamy, “HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level”, Microelectronics Journal, June 2003. (pdf)

CONFERENCE & WORKSHOP PAPERS

1. W. Huang, K. Skadron, S. Gurumurthi, R. Ribando and M. Stan. “Differetiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design”, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2009. (pdf)

2. W. Huang, M. Stan, K. Sankaranarayanan, R. Ribando and K. Skadron. “Many-Core Design from a Thermal Perspective”, Design Automation Conference (DAC), June 2008. (pdf)

3. W. Huang, K. Sankaranarayanan, R. Ribando, M. Stan, K. Skadron. “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations”, WDDD workshop held in conjunction with International Symposium on Computer Architecture (ISCA), June 2007. (pdf)

4. Z. Qi, W. Huang, A. Cabe, W Wu, Y Zhang, G. Rose, M. R. Stan. “A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors”, IEEE International System-On-Chip Conference (SOCC), Sept. 2006. (pdf)

5. W. Huang, E. Humenay, K. Skadron and M. Stan. “The Need for a Full-Chip and Package Thermal Model for Thermally Optimized IC Designs”. Intl. Symp. on Low Power Electronic Design (ISLPED), August 2005. (pdf)

6. S. Velusamy,W. Huang, John Lach, Mircea R. Stan, Kevin Skadron, “Monitoring temperature in FPGA based SoCs” International Conference on Computer Design (ICCD), Oct. 2005. (pdf)

7. K.-J. Lee, K. Skadron and W. Huang. “Analytical model for sensor placement on microprocessors” International Conference on Computer Design (ICCD), Oct. 2005. (pdf)

8. S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for Temperature-Aware Microarchitecture Research.” Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005. (pdf)

9. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron. “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design”. International Conference on Computer Aided Design (ICCAD), November 2004. (pdf)

10. W. Huang, M. R. Stan, and K. Skadron. “Physically-Based Compact Thermal Modeling -Achieving Parameterization and Boundary Condition Independence.” International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2004. (pdf)

11. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. “Compact Thermal Modeling for Temperature-Aware Design”. Design Automation Conference (DAC), June 2004. (pdf)

12. K. Skadron, M.R. Stan, W. Huang, K. Sankaranarayanan, Z. Lu, and J. Lach. “The Need for a Computer-Architecture Approach to Thermal Management in Computer Systems.” IEEE International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Microsystems (EuroSimE), May 2004. (Keynote presentation within session.) (pdf)

13. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Microarchitecture”. International Symposium on Computer Architecture (ISCA), June 2003. (Best Student Paper Award) (pdf)

14. K. Skadron, M. Stan, M. Barcella, A. Dwarka,W. Huang, Y. Li, Y. Ma, A. Naidu, D. Parikh, P. Re, G. Rose, K. Sankaranarayanan, R. Suryanarayan, S. Velusamy, H. Zhang, Y. Zhang. “HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level”. International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2002. (pdf)

TECHNICAL REPORTS

1. W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective: Extended Analysis and Results”, CS-2008-05, April 2008. (pdf)

2. W. Huang; K. Sankaranarayanan; R. J. Ribando; M. R. Stan; K. Skadron. “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations”, CS-2007-07, April, 2007. (pdf)

3. E Humenay, W Huang, MR Stan, K Skadron, “Toward an Architectural Treatment of Parameter Variations”, CS-2005-16, October, 2005. (pdf)

4. S. Velusamy; W. Huang; J. Lach; K. Skadron. “Monitoring Temperature in FPGA based SoCs”, CS-2004-39, December, 2004. (pdf)

5. W. Huang; M. R. Stan; K. Skadron; K. Sankaranarayanan; S. Ghosh; S. Velusamy. “Compact Thermal Modeling for Temperature-Aware Design”, CS-2004-13, April 2004. (pdf)

6. Z. Lu; W. Huang; S. Ghosh; J. Lach; M. R. Stan; K. Skadron. “Analysis of Temporal and Spatial Temperature Gradients for IC Reliability”, CS-2004-08, March 22, 2004. (pdf)

7. W. Huang; Z. Lu; S. Ghosh; J. Lach; M. Stan; K. Skadron. “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis”, CS-2004-07, January 6, 2004. (pdf)

8. K. Skadron; M. R. Stan; W. Huang; S. Velusamy; K. Sankaranarayanan; D. Tarjan. “Temperature-Aware Microarchitecture: Extended Discussion and Results”, CS-2003-08, April 2003. (pdf)

9. M. Barcella, W. Huang, M. R. Stan, K. Skadron, “Architecture-Level Compact Thermal R-C Modeling”, CS-2002-20, July 2002. (pdf)